Patents by Inventor Mordechay Farkash

Mordechay Farkash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Advanced multilayer coreless support structures and method for their fabrication
    Patent number: 7682972
    Abstract: A method of fabricating a free standing membrane including via array in a dielectric for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing laminated array, followed by terminating.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: March 23, 2010
    Assignee: Amitec-Advanced Multilayer Interconnect Technoloiges Ltd.
    Inventors: Dror Hurwitz, Mordechay Farkash, Eva Igner, Boris Statnikov, Benny Michaeli
  • Coreless cavity substrates for chip packaging and their fabrication
    Patent number: 7669320
    Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: March 2, 2010
    Assignee: Amitec-Advanced Multilayer Interconnect Technologies Ltd.
    Inventors: Dror Hurwitz, Mordechay Farkash, Eva Igner, Boris Statnikov, Benny Michaeli
  • CORELESS CAVITY SUBSTRATES FOR CHIP PACKAGING AND THEIR FABRICATION
    Publication number: 20070289127
    Abstract: A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.
    Type: Application
    Filed: April 19, 2007
    Publication date: December 20, 2007
    Applicant: Amitec- Advanced Multilayer Interconnect Technologies LTD
    Inventors: Dror HURWITZ, Mordechay FARKASH, Eva IGNER, Boris STATNIKOV, Benny MICHAELI
  • Advanced Multilayered Coreless Support Structures and their Fabrication
    Publication number: 20070281471
    Abstract: A method of fabricating a free standing membrane comprising a via array in a dielectric for use as a precursor in the construction of superior electronic support structures, comprising the stages: I—Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier, and II—Detaching the membrane from the sacrificial carrier to form a free standing laminated array, and a method of fabricating an electronic substrate based on such a membrane comprising at least the stages of: (I) Fabricating a membrane comprising conductive vias in a dielectric surround on a sacrificial carrier; (II) Detaching the membrane from the sacrificial carrier to form a free standing laminated array; (V) Thinning and planarizing, and (VII) Terminating.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 6, 2007
    Inventors: Dror Hurwitz, Mordechay Farkash, Eva Igner, Boris Statnikov, Benny Michaeli