Abstract: In one embodiment, a navigation system may include at least one self-describing fiducial with a communication element to communicate navigation state estimation aiding information comprising a geographic position of the self-describing fiducial with respect to one or more coordinate systems and a first navigating object to receive navigation information from an exterior system, receive navigation state estimation aiding information from the self-describing fiducial, and compare the navigation information received from the exterior system to the navigation state estimation aiding information to improve navigation parameters of the first navigating object.

Abstract: The present invention is circuitry which is employed with a data terminal which data terminal in turn is part of a system including a main data processor. The present circuitry includes a microprocessor which is connected to the main data processor and to the keyboard. The microprocessor processes signals from both the main data processor and the keyboard. The system has a plurality of operational function circuits, such as a circuit to effect smooth scrolling on a data display means. There is logic circuitry connected between the microprocessor and the operational function circuits. The logic circuitry provides a first path which permits signals, generated in response to instructions from the main data processor, to pass therethrough to select one of the operational function circuits and simultaneously therewith to turn the selected circuit either on or off.

Abstract: The present invention is related to clearing a communication path and in the alternative blocking said communication path between a data terminal and a main data processor, when it appears, from said terminal end, that the data path into the main computer is blocked by some system irregularity in a first case, or should be blocked because of a data overflow condition, in a second case. The present system employs a pair of buffers, the first of which is connected in said communication path, while the second buffer is connected in a data path along which data signals are transmitted from the main data processor. Said communication path includes first logic circuitry connected between said first buffer device and a UART which is connected to the main data processor. Said first logic circuitry can block or unblock the transmission of data to the main data processor. Second logic circuitry is connected between the second buffer and said UART.