Abstract: A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Abstract: A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: The present invention is directed to an Video Processing Engine that is an Overlay Filter Scaler (OFS) having a memory to memory video signal processor decoupled from the display that is better able to meet the feature requirements of a computer graphics system while simplifying the design. The memory-to-memory operation of the video signal processor also facilitates the display of more than one video stream by allowing processed images to be placed in the primary graphics buffers for display. This is particularly useful in video conferencing applications, and for displaying multiple live “thumbnails” of various video feeds. In addition, the signal processor can be used as a graphics anti-aliasing filter by having it process 2-D and 3-D computer graphics images before they are written to the primary display buffer. Similarly, the signal processor can also be used as a “stretch-blitter”, to expand or contract graphics as needed.

Abstract: A method of assigning priorities and resolving bus contention in a distributed computer system is disclosed. Each system node is assigned an identifier. Priorities are reassigned at each change in bus access such that the node that most recently had access to the bus is assigned the lowest priority with the node having the next identifier in sequence being assigned the highest priority and all other nodes assigned priority in accordance with their identifier's position in the sequence. The identifiers are logically treated as organized in a circular fashion such that the lowest node identifier is considered to come next in the sequence after the highest node identifier.

Abstract: A memory for use in a digital data system stores n-bit words, and provides for accessing any group of n contiguous bits, regardless of whether aligned on an n-bit boundary. Barrel shifters facilitate rotating the retrieved bits so as to align them as convenient.