Abstract: A thin film battery comprises a glass or ceramic substrate having a coefficient of thermal expansion (“CTE”) of from about 7 to about 10 ppm/° K, a continuous metal or metal oxide cathode current collector and having a thickness of less than about 3 micrometers, the cathode current collector being superjacent to the glass or ceramic substrate, a cathode material layer comprising lithium transition metal oxides that is a continuous film having a thickness of from about 10 to about 80 micrometers, the cathode material layer being superjacent to the cathode current collector, a LiPON electrolyte layer superjacent to the cathode material layer and having a thickness of from about 0.5 to about 4 micrometers, and an anode current collector with an optional anode material. Methods of making and using the batteries are described.

Abstract: A thin film battery comprises a glass or ceramic substrate having a coefficient of thermal expansion (“CTE”) of from about 7 to about 10 ppm/° K, a continuous metal or metal oxide cathode current collector and having a thickness of less than about 3 micrometers, the cathode current collector being superjacent to the glass or ceramic substrate, a cathode material layer comprising lithium transition metal oxides that is a continuous film having a thickness of from about 10 to about 80 micrometers, the cathode material layer being superjacent to the cathode current collector, a LiPON electrolyte layer superjacent to the cathode material layer and having a thickness of from about 0.5 to about 4 micrometers, and an anode current collector with an optional anode material. Methods of making and using the batteries are described.

Abstract: The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Abstract: The present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therein, or depending on the device, therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.

Abstract: The invention provides a method of planarizing an irregular surface of a semiconductor wafer. In one embodiment, the method comprises applying a photoresist material over recessed areas and protruding areas of the irregular surface, etching the photoresist, etching partially into protruding areas of the irregular surface to remove a portion of the irregular surface, and polishing the irregular surface to a substantially planar surface. In some embodiments method may include chemically and mechanically polishing the irregular surface.

Abstract: The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Abstract: The present invention provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.

Abstract: A method for forming a bipolar transistor is disclosed. An optional thin screen oxide (.apprxeq.150 .ANG.) may be formed upon a substrate over an already-defined collector region. A BF.sub.2 or other implantation is performed through the screen oxide to create the base. The screen oxide is removed and replaced with a patterned high pressure oxide so that the emitter may be defined. The resulting device has a more controllable Gummel number and breakdown voltage.

Abstract: In a method of fabricating semiconductor integrated circuits, the effects of mobile ion contamination in a dielectric layer which has been subjected to a source of mobile ion contamination, e.g., reactive ion etching, is substantially eliminated by removing substantially only the topmost portion of the dielectric layer, e.g., 10-15 nm of an 800 nm layer, promptly after performing the step which produced the source of contamination.

Abstract: Mobile ion concentrations are measured in thick and disordered oxides by heating to a temperature greater than about 250.degree. C.; using a triangular voltage sweep-like method with applied voltages substantially greater than normally used heretofore; and observing peak displacement currents at voltages, e.g., greater than 60 volts, substantially greater than zero volts.