Abstract: A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer test system includes an interposer having a first surface and a second surface facing away from the first surface. The system also includes a wafer translator having a first side facing the second surface of the interposer and a second side facing away from the first side and toward a wafer, the first side carrying a plurality of first terminals at a first scale and the second side carrying a plurality of second terminals at a second scale. The first scale is greater than the second scale.

Abstract: A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between

Abstract: An apparatus includes a processor having an array of processor interconnects arranged to connect the processor to conductive paths, a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects, an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate, and at least one peripheral circuit connected to the at least one conductive trace.

Abstract: An apparatus includes a processor having an array of processor interconnects arranged to connect the processor to conductive paths, a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects, an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate, and at least one peripheral circuit connected to the at least one conductive trace.

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer test system includes an interposer having a first surface and a second surface facing away from the first surface. The system also includes a wafer translator having a first side facing the second surface of the interposer and a second side facing away from the first side and toward a wafer, the first side carrying a plurality of first terminals at a first scale and the second side carrying a plurality of second terminals at a second scale. The first scale is greater than the second scale.

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.

Abstract: An apparatus includes a processor having an array of processor interconnects arranged to connect the processor to conductive paths, a circuit substrate having an array of circuit interconnects arranged to provide connections between the processor and the circuit substrate, the circuit substrate having conductive paths connected to the array of circuit interconnects, an interposer substrate arranged between the processor and the circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one processor interconnect in the array of interconnects on the processor, the conductive trace arranged at least partially parallel to the interposer substrate such that no electrical connection exists between the conductive trace in the interposer substrate and a corresponding one of the circuit interconnects on the circuit substrate, and at least one peripheral circuit connected to the at least one conductive trace

Abstract: A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects.

Abstract: A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects.

Abstract: A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, and peripheral circuit modules residing on the interposer substrate, wherein each peripheral circuit module has an electrical path having a path length to the main processor less than one-quarter of a wavelength of signals that will travel the electrical path.

Abstract: A wafer testing system and associated methods of use and manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.

Abstract: A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.

Abstract: A wafer testing system and associated methods of use an manufacture are disclosed herein. In one embodiment, the wafer testing system includes an assembly for releaseably attaching a wafer to a wafer translator and the wafer translator to an interposer by means of separately operable vacuums, or pressure differentials. The assembly includes a wafer translator support ring coupled to the wafer translator, wherein a first flexible material extends from the wafer translator support ring so as to enclose the space between the wafer translator and the interposer so that the space may be evacuated by a first vacuum through one or more first evacuation paths. The assembly can further include a wafer support ring coupled to the wafer and the chuck, wherein a second flexible material extends from wafer support ring so as to enclose the space between the wafer and the wafer translator so that the space may be evacuated by a second vacuum through one or more second evacuation pathways.

Abstract: Translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods are disclosed. An arrangement in accordance with one embodiment includes a microelectronic substrate having a first major surface, a second major face facing opposite from the first major surface, and electrically conductive through-substrate vias extending through the substrate and electrically accessible from both the first and second surfaces.

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract: A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, at least one peripheral circuit on the interposer substrate, and a heat sink thermally coupled to the peripheral circuit.

Abstract: A computing device has a circuit substrate having a socket, a main processor inserted into the socket, an interposer substrate inserted between the socket and the main processor, the circuit substrate, the socket and the interposer substrate being electrically connected, and peripheral circuit modules residing on the interposer substrate, wherein each peripheral circuit module has an electrical path having a path length to the main processor less than one-quarter of a wavelength of signals that will travel the electrical path.

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract: A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.