Abstract: Many computer processing tasks require large numbers of memory intensive operations to be performed very rapidly. For example, computer network requires that packets be placed into and removed from First-In First-Out (FIFO) queues, numerous counters to be maintained and routing table look-ups to be performed. All of these operations must be performed at very high-speeds in order to keep up with today's high-speed computer network traffic. To help perform these high-speed memory tasks, a high-speed intelligent memory subsystem has been developed. The high-speed intelligent memory subsystem handles the intricacies of these memory operations such that a main process is relieved of some of its duties. Various different high-level memory interfaces for interfacing with the intelligent memory subsystem. The memory interfaces may be hardware-based or software-based.

Abstract: A method of estimating end-to-end delay performance at an end-to-end delay percentile of interest for a network having two or more network segments includes measuring a delay performance level for each network segment at a corresponding network segment delay percentile and concatenating the measured performance levels by summing to provide an estimate value indicative of end-to-end delay performance. A network segment delay percentile may be selected for each network segment for a particular end-to-end delay percentile of interest, error band, and number of segments. Selection may result in using the same network segment delay percentile for all network segments, or, selecting individual network segment delay percentiles for each network segments, or selecting a first network segment delay percentile for a particular network segment having a largest range of delay relative to the other network segments and selecting a second network segment delay percentile for other segments.

Abstract: The present invention introduces various high-level memory interfaces for interfacing with an intelligent memory system. The memory interfaces may be hardware-based or software-based. In one embodiment, two layers of interfaces are implemented such that an internal interface may evolve over successive generations without affecting an externally visible interface.

Abstract: A novel packet switch architecture is disclosed. The packet switch utilizes internal queuing (i.e. recirculation loops) and output queuing (i.e. multiple paths to each destination) to provide a packet switch which offers superior performance in comparison to a packet switch which utilizes either of these queuing strategies alone. The combination of recirculation and output queues have complimentary effects. The output queuing reduces the number of recirculation loops needed and recirculation reduces the bandwidth requirements for an output buffered switch.

Abstract: A communications switch comprises a multi-layer switch configuration each layer comprising a synchronized packet switch with a pre-circulation stage 12, circulation re-entry stage 14, intermediate stage 16, re-circulation exit stage 17 and final exit stage 18. A re-circulation stage 15 allows re-circulation of data from one synchronized packet switch to another synchronized packet switch via paths 35. A number of switch input nodes 32 and output nodes 34 have accesss to each of the synchronized packet switches.