Abstract: In one embodiment, one or more computing systems may determine a first display content to be displayed on a display. The first display content may be associated with one or more frames. The one or more computing systems may determine an optimization operation for the first display content based on one or more first parameters associated with the display or one or more second parameters associated with the one or more frames. The one or more computing systems may adjust the one or more frames based on the optimization operation. The adjusted one or more frames may have at least one optimized attribute comparing to the one or more frames before being adjusted. The one or more computing systems may output the adjusted one or more frames to the display to represent the first display content.

Abstract: In one embodiment, a computing system may receive one or more signals from one or more sensors associated with an artificial reality system. The system may determine one or more parameters associated a display content for the artificial reality system based on the one or more signals of the one or more sensors associated with the artificial reality system. The system may generate the display content based on the one or more parameters. The system may output the display content to a display of the artificial reality system.

Abstract: A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.

Abstract: A processor is configured to implement an instruction set architecture for accessing data that includes loading data elements from a memory containing data blocks separated by block boundaries. The instruction set architecture includes a first type of data load instruction for loading an aligned data structure from the memory and a second type of data load instruction for loading an unaligned data structure from the memory. The loading includes fetching a data load instruction of the second type and loading from the memory according to the data load instruction of the second type. The resulting data structure formed of n consecutive data elements is determined from the data load instruction. The data structure loaded from memory is formed of n consecutive unaligned data elements. The processor is similarly configured to implement storing data elements from a set of registers to a memory containing data blocks separated by block boundaries.

Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise a variable length instruction set that includes one or more pointer-size controlled memory access instructions of a smaller length (e.g. 16 bits) wherein the size of the data accessed by such an instruction is dynamically determined based on the size of the pointer. Specifically, when a pointer-size controlled memory access instruction is received at a decode unit, the decode unit outputs one or more control signals to cause an execution unit to perform a memory access of a first size (e.g. 32 bits) when the pointer size is the first size (e.g. 32 bits), and output one or more control signals to cause the execution unit to perform a memory access of a second size (e.g. 64 bits) when the pointer size is the second size (e.g. 64 bits).

Abstract: Instruction set architectures (ISAs) and apparatus and methods related thereto comprise an instruction set that includes one or more instructions which identify the global pointer (GP) register as an operand (e.g., base register or source register) of the instruction. Identification can be implicit. By implicitly identifying the GP register as an operand of the instruction, one or more bits of the instruction that were dedicated to explicitly identifying the operand (e.g., base register or source register) can be used to extend the size of one or more other operands, such as the offset or immediate, to provide longer offsets or immediates.

Abstract: Described herein are instruction set architectures (ISAs), and related data processing apparatuses and methods, with two or more non-contiguous blocks of preserved registers wherein the registers to be saved or restored are identified in a save or restore instruction via a number of registers to be saved/restored (Num_Reg) and a starting register (rStart). Specifically, in the ISAs, apparatuses, and methods described herein, the registers to be saved or restored are identified as the Num_Reg registers in a predetermined sequence starting with rStart wherein, in the predetermined sequence, each register is followed by the next highest numbered register except the highest numbered preserved register, which is followed by the lowest numbered preserved register.

Abstract: A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.

Abstract: An image processing system is described herein in which a multi-line processing block has multiple inputs and multiple outputs. In order to provide the multiple outputs the multi-line processing block has multiple processing units operating in parallel on the multiple inputs. The multiple outputs of the multi-line processing block are coupled to corresponding multiple inputs of a subsequent multi-line processing block in the image processing system.

Abstract: An image processing system is described herein in which a multi-line processing block has multiple inputs and multiple outputs. In order to provide the multiple outputs the multi-line processing block has multiple processing units operating in parallel on the multiple inputs. The multiple outputs of the multi-line processing block are coupled to corresponding multiple inputs of a subsequent multi-line processing block in the image processing system.

Abstract: An image processing system is described herein in which a multi-line processing block has multiple inputs and multiple outputs. In order to provide the multiple outputs the multi-line processing block has multiple processing units operating in parallel on the multiple inputs. The multiple outputs of the multi-line processing block are coupled to corresponding multiple inputs of a subsequent multi-line processing block in the image processing system.

Abstract: An image processing system is described herein in which a multi-line processing block has multiple inputs and multiple outputs. In order to provide the multiple outputs the multi-line processing block has multiple processing units operating in parallel on the multiple inputs. The multiple outputs of the multi-line processing block are coupled to corresponding multiple inputs of a subsequent multi-line processing block in the image processing system.

Abstract: A microprocessor architecture including a unified cache debug unit. A debug unit on the processor chip receives data/command signals from a unit of the execute stage of the multi-stage instruction pipeline of the processor and returns information to the execute stage unit. The cache debug unit is operatively connected to both instruction and data cache units of the microprocessor. The memory subsystem of the processor may be accessed by the cache debug unit through either of the instruction or data cache units. By unifying the cache debug in a separate structure, the need for redundant debug structure in both cache units is obviated. Also, the unified cache debug unit can be powered down when not accessed by the instruction pipeline, thereby saving power.