Abstract: A modulator that effectively suppresses carrier leakage is disclosed. The modulator includes a frequency multiplier, a phase shifter and an orthogonal modulator. The frequency multiplier outputs complementary signals whose frequencies are twice the frequency of a first carrier signal. The phase shifter divides the frequencies of the output signals of the frequency multiplier to produce a plurality of second carrier signals whose phases are shifted by 90 degrees from one another. The orthogonal modulator receives an input signal and the second carrier signals from the phase shifter and outputs signals obtained by combining the input signal with the second carrier signals. The frequency multiplier has an input circuit section including a differential circuit. The differential input section receives complementary signals as the first carrier signal. The orthogonal modulator has an output circuit section including a differential circuit.

Abstract: A constant voltage circuit adapted for connection between high voltage power source and low voltage power source terminals respectively to output a constant voltage signal from an output terminal in response to a control signal inputted to an input terminal. The circuit has a resistor circuit including a MOS transistor for connection to the high voltage power source and activated in response to the control signal. A current mirror section is connected between the resistor circuit and the low voltage power source terminal to generate an output voltage to be outputted from the output terminal. A feedback section is connected between the resistor circuit and the low voltage power source terminal to control the current mirror section to keep the output voltage constant by detecting deviation of the output voltage.

Abstract: An input signal is provided at first input terminals of a plurality of parallel AND gates in a delay time control circuit. A digital signal from a decoder having a plurality of bits is coupled to second input terminals of the AND gates with one bit coupled per AND gate. The decoder outputs a signal having an a high level in response to an external input control signal. Output signals from the AND gates are coupled to inputs of a plurality of serially connected OR gates.

Abstract: A level converting circuit converts a first signal which has an ECL level which is used in an ECL device into a second signal which has a GaAs logic level which is used in a GaAs device which is based on a GaAs substrate.

Abstract: A circuit has a level converting circuit for converting a signal having level in conformance with a first logic system into a signal having a level in conformance with a second logic system.