Patents by Inventor Morikazu Tsuno
Morikazu Tsuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240349525Abstract: An imaging device includes a photoelectric converter that converts incident light to charge, a semiconductor substrate that includes an element isolation region and a first impurity region of a first conductivity type, the first impurity region being electrically connected to the photoelectric converter, a plug that includes a first semiconductor, the plug being connected directly to the first impurity region, a pad that includes a second semiconductor, the pad being connected directly to the plug, and a first transistor that includes the first impurity region as one of a source and a drain and includes a first gate. The first impurity region is positioned between the first gate and a first portion of the element isolation region in plan view. The pad overlaps the first gate and the first portion in plan view.Type: ApplicationFiled: June 25, 2024Publication date: October 17, 2024Inventor: Morikazu TSUNO
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Patent number: 12107096Abstract: An imaging device includes a photoelectric conversion layer, a counter electrode provided above the photoelectric conversion layer, a pixel electrode that faces the counter electrode with the photoelectric conversion layer disposed between the counter electrode and the pixel electrode, and a contact plug covered with the pixel electrode and connected to the pixel electrode. The pixel electrode includes a first layer and a second layer provided on the first layer in contact with the first layer. A surface of the first layer that is in contact with the second layer has a protrusion that protrudes upward.Type: GrantFiled: April 16, 2021Date of Patent: October 1, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Morikazu Tsuno, Takanori Doi, Yoshinori Takami
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Patent number: 12048171Abstract: An imaging device includes a photoelectric converter that converts incident light to charge, a semiconductor substrate that includes an element isolation region and a first impurity region of a first conductivity type, the first impurity region being electrically connected to the photoelectric converter, a plug that includes a first semiconductor, the plug being connected directly to the first impurity region, a pad that includes a second semiconductor, the pad being connected directly to the plug, and a first transistor that includes the first impurity region as one of a source and a drain and includes a first gate. The first impurity region is positioned between the first gate and a first portion of the element isolation region in plan view. The pad overlaps the first gate and the first portion in plan view.Type: GrantFiled: June 1, 2021Date of Patent: July 23, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Morikazu Tsuno
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Publication number: 20230290793Abstract: An imaging device includes: a photoelectric converter that generates a signal charge by photoelectric conversion; a semiconductor substrate that includes a first semiconductor layer containing an impurity of a first conductivity type; a charge accumulation region that is an impurity region of a second conductivity type in the first semiconductor layer and that accumulates the signal charge; a transistor that includes, as one of a source and a drain, a first impurity region of the second conductivity type in the first semiconductor layer; and a blocking structure located between the charge accumulation region and the first impurity region. The blocking structure includes a second impurity region of the first conductivity type in the first semiconductor layer and a third impurity region of the first conductivity type in the first semiconductor layer, the third impurity region having an impurity concentration different from that of the second impurity region.Type: ApplicationFiled: May 15, 2023Publication date: September 14, 2023Inventors: MORIKAZU TSUNO, JUNJI HIRASE
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Publication number: 20210351212Abstract: An imaging device includes a photoelectric conversion layer, a counter electrode provided above the photoelectric conversion layer, a pixel electrode that faces the counter electrode with the photoelectric conversion layer disposed between the counter electrode and the pixel electrode, and a contact plug covered with the pixel electrode and connected to the pixel electrode. The pixel electrode includes a first layer and a second layer provided on the first layer in contact with the first layer. A surface of the first layer that is in contact with the second layer has a protrusion that protrudes upward.Type: ApplicationFiled: April 16, 2021Publication date: November 11, 2021Inventors: MORIKAZU TSUNO, TAKANORI DOI, YOSHINORI TAKAMI
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Publication number: 20210288115Abstract: An imaging device includes a photoelectric converter that converts incident light to charge, a semiconductor substrate that includes an element isolation region and a first impurity region of a first conductivity type, the first impurity region being electrically connected to the photoelectric converter, a plug that includes a first semiconductor, the plug being connected directly to the first impurity region, a pad that includes a second semiconductor, the pad being connected directly to the plug, and a first transistor that includes the first impurity region as one of a source and a drain and includes a first gate. The first impurity region is positioned between the first gate and a first portion of the element isolation region in plan view. The pad overlaps the first gate and the first portion in plan view.Type: ApplicationFiled: June 1, 2021Publication date: September 16, 2021Inventor: MORIKAZU TSUNO
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Publication number: 20200105823Abstract: An imaging device includes a semiconductor substrate and a pixel. The semiconductor substrate includes first and second surfaces that oppose each other, a first region containing an impurity of a first conductivity type, a second region that contains an impurity of a second conductivity type and that is closer to the first surface than the first region is, a third region that contains an impurity of the first conductivity type and that is closer to the first surface than the second region is, and a fourth region that provides connection between the first and third regions and that contains an impurity of the first conductivity type. The pixel includes a photoelectric converter, and a first diffusion region that is electrically connected to the photoelectric converter, that is located in the third region, that is exposed at the first surface, and that overlaps the entire first diffusion region in plan view.Type: ApplicationFiled: September 11, 2019Publication date: April 2, 2020Inventor: MORIKAZU TSUNO
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Patent number: 10600840Abstract: An imaging device includes a semiconductor substrate and a pixel. The semiconductor substrate includes first and second surfaces that oppose each other, a first region containing an impurity of a first conductivity type, a second region that contains an impurity of a second conductivity type and that is closer to the first surface than the first region is, a third region that contains an impurity of the first conductivity type and that is closer to the first surface than the second region is, and a fourth region that provides connection between the first and third regions and that contains an impurity of the first conductivity type. The pixel includes a photoelectric converter, and a first diffusion region that is electrically connected to the photoelectric converter, that is located in the third region, that is exposed at the first surface, and that overlaps the entire first diffusion region in plan view.Type: GrantFiled: September 11, 2019Date of Patent: March 24, 2020Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventor: Morikazu Tsuno
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Patent number: 7939859Abstract: A solid state imaging device includes a transfer transistor for transferring signal charges generated by photoelectric conversion to a floating diffusion layer, a reset transistor for resetting a potential of the floating diffusion layer, and an amplifying transistor for outputting a signal corresponding to the potential of the floating diffusion layer. A low concentration impurity region having an impurity concentration lower than that of the first conductivity type semiconductor region is formed in part of a surface portion of the first conductivity type semiconductor region which is located below a gate electrode of the amplifying transistor and serves as a well region of the amplifying transistor.Type: GrantFiled: March 20, 2009Date of Patent: May 10, 2011Assignee: Panasonic CorporationInventor: Morikazu Tsuno
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Publication number: 20100308384Abstract: A photodiode has a carrier accumulation layer of a second conductivity type and a surface area of a first conductivity type deposited in order from an inside towards a surface of a first conductivity type well region. A transfer transistor is formed so that a transfer gate electrode of the transfer transistor partially overlaps the surface layer of the photodiode and is formed above a surface of the first conductivity type well region with a gate insulating film therebetween. The surface layer includes a first surface layer, which partially overlaps the transfer gate electrode in the direction of the x-axis, and a second surface layer adjacent to the first surface layer. A concentration of the impurity of the first conductivity type is higher in the second surface layer than in the first surface layer.Type: ApplicationFiled: April 27, 2010Publication date: December 9, 2010Inventors: Morikazu TSUNO, Keishi TACHIKAWA
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Publication number: 20090289282Abstract: A solid state imaging device includes a transfer transistor for transferring signal charges generated by photoelectric conversion to a floating diffusion layer, a reset transistor for resetting a potential of the floating diffusion layer, and an amplifying transistor for outputting a signal corresponding to the potential of the floating diffusion layer. A low concentration impurity region having an impurity concentration lower than that of the first conductivity type semiconductor region is formed in part of a surface portion of the first conductivity type semiconductor region which is located below a gate electrode of the amplifying transistor and serves as a well region of the amplifying transistor.Type: ApplicationFiled: March 20, 2009Publication date: November 26, 2009Inventor: Morikazu TSUNO
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Publication number: 20070087518Abstract: A method for forming STIs in a semiconductor substrate includes forming a protective oxide film on the semiconductor substrate and forming a silicon nitride film on the protective oxide film, performing a photolithography and a dry etching so as to penetrate the silicon nitride film and the protective oxide film and remove part of the semiconductor substrate, thus forming groove portions, forming a buried oxide film in the groove portions and on the silicon nitride film, removing the buried oxide film on the silicon nitride film and a surface portion of the silicon nitride film by a CMP, and removing part of the buried oxide film deposited in the groove portions by a wet etching. It is possible to provide a method for producing STIs capable of forming uniform STI step heights in a semiconductor device with a fine structure.Type: ApplicationFiled: August 11, 2006Publication date: April 19, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mototaka OCHI, Morikazu TSUNO
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Publication number: 20070026544Abstract: The as-implanted concentration profile of impurity atoms in the semiconductor substrate is calculated, and a number of interstitial atoms to be generated in the semiconductor substrate by one impurity atom implanted with the ion implantation is set based on a peak concentration of the calculated as-implanted concentration profile of impurity atoms. The concentration profile of interstitial atoms generated in the semiconductor substrate is calculated based on the calculated as-implanted concentration profile of impurity atoms and the set number of interstitial atoms, and the concentration profile of impurity atoms in the semiconductor after the thermal processing is calculated based on the calculated as-implanted concentration profile of impurity atoms and the calculated concentration profile of interstitial atoms.Type: ApplicationFiled: July 6, 2006Publication date: February 1, 2007Inventor: Morikazu Tsuno