Patents by Inventor Morio Nakao

Morio Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7568922
    Abstract: This invention provides a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad comprises pad portion loaded with solder ball and a cylindrical portion projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: August 4, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Takahiro Yamashita, Hiroyuki Watanabe, Kiyotaka Tsukada, Michio Ido, Morio Nakao
  • Publication number: 20060169484
    Abstract: This invention provides a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad comprises pad portion loaded with solder ball and a cylindrical portion projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball.
    Type: Application
    Filed: December 16, 2005
    Publication date: August 3, 2006
    Applicant: IBIDEN CO., LTD.
    Inventors: Takahiro Yamashita, Hiroyuki Watanabe, Kiyotaka Tsukada, Michio Ido, Morio Nakao
  • Publication number: 20050023682
    Abstract: A packaged chip-scale semiconductor device (400) has a substrate with a patterned metal layer (202) and first and second surfaces (202a and 202b, respectively). The first portion of an insulating material (305a) fills the spaces of the patterned metal layer. The second portion (401) of the insulating material is attached to the first surface (202a) of the patterned metal layer, forming a plurality of windows (402) to expose the metal for connection to external parts; around the periphery of these windows, the insulating material (401) preferably has a thickness of less than 30 ?m. The third portion (205) of the insulating material forms, on the second surface (202b) of the patterned metal layer, a layer with an area suitable for attaching an integrated circuit chip (206). Solder balls attached to the metal surfaces exposed in the windows (402) have solder necks after reflow preferably less than 30 ?m long, which helps avoid a solder separation problem induced by surface tension.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 3, 2005
    Inventor: Morio Nakao
  • Publication number: 20040036172
    Abstract: A packaged integrated circuit including a substrate 410 having opposing top and bottom surfaces and a chip 400 having opposing active and bottom surfaces. The chip is mounted on the top surface of the substrate such that the bottom surface of the chip is adjacent to the substrate, and such that the active surface of the chip is away from the substrate. The packaged integrated circuit also includes a thermally-conductive interposer 460 mounted on the active surface of the chip and a heatspreader 470 over the interposer. The interposer can be in contact with or attached to the heatspreader.
    Type: Application
    Filed: August 26, 2002
    Publication date: February 26, 2004
    Inventors: Chikara Azuma, Morio Nakao
  • Patent number: 6232558
    Abstract: An electronic component mounting base board has an insulating substrate provided with a conductor circuit and a mount portion for an electronic component, and a heat slug adhered to the insulating substrate, wherein the heat slug is comprised of a flat main body and a projection portion extending vertically from a side face of the main body, and provided with a slit deforming portion absorbing deformation of the insulating substrate.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: May 15, 2001
    Assignees: Ibiden Co., Ltd., Texas Instruments Incorporated
    Inventors: Kiyotaka Tsukada, Hisashi Minoura, Koji Asano, Naoto Ishida, Morio Nakao
  • Patent number: 5914859
    Abstract: An electronic component mounting base board comprises an insulating substrate provided with a mounting portion for mounting an electronic component and a heat-sink plate disposed on an lower surface of the insulating substrate, in which the insulating substrate is provided with a wiring pattern for signal or power, a grounding pattern and a grounding hole, and the grounding hole is provided on its inner wall with a metal plated film for electrically connecting to the grounding pattern and a solder is filled in an inside of the grounding hole for electrically connecting to the heat-sink plate.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: June 22, 1999
    Assignees: Ibiden Co., Ltd., Texas Instruments Japan, Ltd.
    Inventors: Masaru Takada, Kiyotaka Tsukada, Morio Nakao