Patents by Inventor Morito Rokuda

Morito Rokuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5063437
    Abstract: This invention relates to a method and apparatus for processing a color video signal.
    Type: Grant
    Filed: April 28, 1989
    Date of Patent: November 5, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hitoaki Owashi, Hiroyasu Ohtsubo, Masataka Sekiya, Kohji Minabe, Hideo Nishijima, Michio Masuda, Morito Rokuda
  • Patent number: 4855812
    Abstract: A picture synthesizing apparatus in which a main picture is displayed with a part inlaid with a subsidiary picture. The apparatus includes an AGC circuit for regulating the gain of the main video signal and an AGC circuit for regulating the gain of a subsidiary video signal. Alternatively, the chrominance signal level of the subsidiary video signal can be regulated in accordance with the chrominance signal level of the main video signal.
    Type: Grant
    Filed: December 15, 1987
    Date of Patent: August 8, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Morito Rokuda, Hiroyasu Ohtsubo, Michio Masuda, Hideo Nishijima, Kaneyuki Okamoto
  • Patent number: 4700240
    Abstract: Number data affixed to individual digital data divided into a plurality of data blocks are sequentially read out from a recording medium to be used for determining the write-in positions of the digital data in a memory. For determining the write-in positions of the digital data, the number data of the next write-in position is estimated on the basis of the number data of the current write-in position. Judgment is made as to whether or not the number of times of continuous non-coincidence between the estimated number data and the successively read-out number data exceeds a predetermined setting, and, also judgment is made as to whether or not the number data read out each time falls within a predetermined range. Depending on the results of these judgments, one of the read-out number data and the estimated number data is selected to determine the next write-in position.
    Type: Grant
    Filed: November 5, 1985
    Date of Patent: October 13, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Masuo Umemoto, Yoshizumi Eto, Hidehiro Kanada, Morito Rokuda
  • Patent number: 4682115
    Abstract: An apparatus for regenerating original signals comprising: means for introducing a first signal that is produced as an original signal passes through a system that cuts off predetermined frequencies; a first circuit means which produces a third signal obtained on an open loop responsive to said first signal and a second signal which is regenerated from a signal of a predetermined frequency that is cut off by said system; and a second circuit means which regenerates the original signal by converting said third signal into a binary signal.
    Type: Grant
    Filed: June 10, 1985
    Date of Patent: July 21, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Seiichi Mita, Morishi Izumita, Yuichi Michikawa, Hitoshi Katayama, Hiroshi Shiono, Hitoshi Takagi, Morito Rokuda, Nobukazu Doi
  • Patent number: 4670797
    Abstract: An improved 8-8 mpping table system in digitally and magnetically recording video signals. Video signals coded into natural binary codes consisting of 8 bits are converted into different binary codes consisting of 8 bits constituted by patterns in which a continuous number of the 1's or the 0's does not exceed a predetermined number. In these codes, the continuous number of the 1's or the 0's is so limited that a maximum magnetization interval is reduced in magnetically recording the signals. Therefore, erroneous code is prevented from occurring in reproducing the signals.
    Type: Grant
    Filed: February 19, 1985
    Date of Patent: June 2, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Masuo Umenoto, Seiichi Mita, Morishi Izumita, Yuuichi Michikawa, Morito Rokuda, Hitoshi Katayama, Hidehiro Kanada
  • Patent number: 4661956
    Abstract: Parity bits (check bits) having a relatively high redundancy are added to upper significant bits of a digital signal, and parity bits having a relatively low redundancy, are added to the lower significant bits of the digital signal. The signal and the parity bits are recorded on a recording medium. The position of an error in a data block group of the lower bits reproduced from the recording medium is estimated as existing in a block in which the error is detected by the check of the data block group of the upper bits, and in the blocks preceding and subsequent to the former.This error correction method is most suitable for a recording and reproduction system of digital video signals.
    Type: Grant
    Filed: February 21, 1985
    Date of Patent: April 28, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Morishi Izumita, Seiichi Mita, Masuo Umemoto, Hidehiro Kanada, Morito Rokuda
  • Patent number: 4653052
    Abstract: The present invention relates to a method and an apparatus for decoding double-encoding codes in which the information to be decoded comprises a first data and a second data. The operation for decoding double-encoding codes is achieved through two stages. A decoder of the first stage checks the first data, and when an error is found in the first data, all symbols of the first data are assumed to be wrong. The first-stage decoder then adds an erasure flag to all symbols to generate erasure symbols. As a result, these erasure symbols include the symbols which are actually erroneous and those which are correct. A decoder of the second stage is used to perform an error correction on the second data. For this purpose, the second-stage decoder detects the number of erasure symbols which are contained in the second data and which are actually erroneous.
    Type: Grant
    Filed: July 1, 1985
    Date of Patent: March 24, 1987
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Nobukazu Doi, Morishi Izumita, Seiichi Mita, Yoshizumi Eto, Morito Rokuda
  • Patent number: 4628297
    Abstract: In the code modulation system for converting input data levels into an output signal in the form of code words by providing M input levels among N input levels assigned to input data with stairlike code weights on the basis of the input levels, (N-M) input levels which are the difference between said N input levels and said M input levels are respectively disposed near transition points where said stairlike code weight is changed, and the code weights are provided with hysteresis in the ascent process and the descent process of the input data level.
    Type: Grant
    Filed: January 30, 1985
    Date of Patent: December 9, 1986
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha
    Inventors: Seiichi Mita, Morishi Izumita, Masuo Umemoto, Yoshizumi Eto, Morito Rokuda, Hidehiro Kanada