Abstract: The present disclosure relates in an aspect to an integrated circuit device. The integrated circuit device comprises an active device tier and a frontside interconnect structure arranged at a frontside of the active device tier and a backside interconnect structure arranged at a backside of the active device tier. The integrated circuit device comprises a plurality of circuit blocks, and a data communication circuit configured to transfer data between the plurality of circuit circuit blocks. The data communication circuit comprises a plurality of switching circuits. Each circuit circuit block is connected to the data communication circuit by a switching circuit. The data communication circuit further comprises a plurality of data communication channels interconnecting the plurality of switching circuits and comprising a plurality of backside interconnects arranged in one or more interconnect layers of the backside interconnect structure.

Abstract: A static random access memory (SRAM) device includes a plurality of bit cells, each bit-cell including a first half-cell and a second half-cell, each half-cell including a first and a second complementary field-effect transistor (CFET) device. Each CFET device includes a bottom device and a top device stacked on top of the bottom device. The first CFET device includes a common gate shared by the bottom device and the top device and is configured as an inverter cross-coupled to the inverter of the other half-cell. The bottom device of the second CFET device is configured as a first pass-gate for a first port of the half-cell. The top device of the second CFET device is configured as a second pass-gate for a second port of the half-cell.