Patents by Inventor Moritz Josef Hoffmann

Moritz Josef Hoffmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10628057
    Abstract: An example computing system may include a plurality of processors, persistent memory that is shared by the plurality of processors, and a memory-side accelerator that is to control access to the memory. A requesting processor of the plurality of processors may simultaneously request locking of and access to a target data object of the persistent memory by sending a single lock-and-access message to the memory-side accelerator. The lock-and-access message may include a first memory capability pointing to the target data object, a second memory capability pointing to a lock object that controls locking of the target data object, and a specified access operation that is requested.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 21, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Alexander Leslie Richardson, Moritz Josef Hoffmann, Dejan S. Milojicic
  • Patent number: 10387335
    Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 20, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Dejan S. Milojicic, Moritz Josef Hoffmann, Alexander Richardson, Qiong Cai
  • Publication number: 20190095356
    Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.
    Type: Application
    Filed: September 28, 2017
    Publication date: March 28, 2019
    Inventors: Dejan S. Milojicic, Moritz Josef Hoffmann, Alexander Richardson, Qiong Cai
  • Publication number: 20180285003
    Abstract: An example computing system may include a plurality of processors, persistent memory that is shared by the plurality of processors, and a memory-side accelerator that is to control access to the memory. A requesting processor of the plurality of processors may simultaneously request locking of and access to a target data object of the persistent memory by sending a single lock-and-access message to the memory-side accelerator. The lock-and-access message may include a first memory capability pointing to the target data object, a second memory capability pointing to a lock object that controls locking of the target data object, and a specified access operation that is requested.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Inventors: Alexander Leslie Richardson, Moritz Josef Hoffmann, Dejan S. Milojicic