Patents by Inventor Moriya Miyashita

Moriya Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887845
    Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 30, 2024
    Assignees: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITY
    Inventors: Kazutaka Kamijo, Etsuo Fukuda, Takashi Ishikawa, Koji Izunome, Moriya Miyashita, Takao Sakamoto, Tetsuo Endoh
  • Publication number: 20220093396
    Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 24, 2022
    Applicants: GLOBALWAFERS JAPAN CO., LTD., TOHOKU UNIVERSITY
    Inventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH
  • Publication number: 20200211840
    Abstract: A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.
    Type: Application
    Filed: July 17, 2018
    Publication date: July 2, 2020
    Applicants: GlobalWafers Japan Co., Ltd., TOHOKU UNIVERSITY
    Inventors: Kazutaka KAMIJO, Etsuo FUKUDA, Takashi ISHIKAWA, Koji IZUNOME, Moriya MIYASHITA, Takao SAKAMOTO, Tetsuo ENDOH
  • Patent number: 7700381
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 20, 2010
    Assignee: Kabushikia Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Publication number: 20060131696
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Application
    Filed: February 9, 2006
    Publication date: June 22, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7057259
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 6, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Publication number: 20030003608
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Application
    Filed: March 20, 2002
    Publication date: January 2, 2003
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 6222252
    Abstract: A semiconductor substrate is provided which can efficiently exhibit intrinsic gettering (IG) effect, is less likely to cause slipping or dislocation, and causes no significant lowering in mechanical strength. The semiconductor substrate has bulk micro defects dispersed at a density of not less than 1011 micro defects/cm3 in the interior thereof.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanori Numano, Moriya Miyashita
  • Patent number: 6037270
    Abstract: The gate oxide film is prevented from being thinned partially. The semiconductor substrate (wafer) can be etched (processed) under excellent conditions. The impurities on the wafer surface can be analyzed and further reduced. In the first aspect, the substrate is irradiated with ultraviolet rays in contact with an F-containing aqueous solution, so that the oxide film and the substrate can be etched at roughly the same etching speed under excellent controllability without deteriorating the planarization of the substrate. In the second aspect, the substrate is etched by irradiating ultraviolet rays during exposure to an acid aqueous solution, so that surface metallic contamination and particles can be removed without deteriorating the wafer surface roughness. Further, the impurity elements in the outermost surface layer of the wafer can be analyzed at high precision by analyzing elements contained in the acid aqueous solution used for the etching.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mokuji Kageyama, Moriya Miyashita
  • Patent number: 5951755
    Abstract: A manufacturing method for manufacturing a semiconductor substrate has first annealing step for annealing silicon single crystal to permit oxygen embryos or oxygen precipitations grown from the oxygen embryos precipitating in a predetermined region and a second annealing step for permitting said oxygen embryos or said oxygen precipitations to contract using a second temperature range higher than the first temperature range, said second temperature range being high enough to contract said oxygen embryos and low enough to prevent redistribution of boron from affecting to device characteristics, to form a denuded zone in said predetermined region at the principal surface. An inspection method for inspecting a semiconductor substrate further has measuring step, subsequent to said first and second annealing steps for measuring the density of oxygen embryos grown into oxygen precipitations among those precipitated in said silicon single crystal.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: September 14, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Masanobu Ogino, Tadahide Hoshi, Masanori Numano, Shuichi Samata, Akiko Sekihara, Keiko Akita
  • Patent number: 5508800
    Abstract: There are provided a method of inspecting and evaluating semiconductor substrates, good quality semiconductor substrates, a method of manufacturing good quality semiconductor substrates, and a method of manufacturing semiconductor devices using good quality semiconductor substrates.A semiconductor substrate is processed with aqueous basic solution. In this process, the substrate is dipped in the aqueous solution or exposed to a vapor of the aqueous solution. With this process, the surface of the substrate is selectively etched. The substrate surface after the etching process is radiated with a laser beam to measure a light scattered point density. The quality of the substrate can be judged in accordance with the measured density. A thermal treatment may be carried out before or after processing the substrate with the aqueous basic solution. The thermal treatment considerably changes the fine defect density on the surface of the substrate.
    Type: Grant
    Filed: March 16, 1993
    Date of Patent: April 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Hachiro Hiratsuka, Atsuko Kubota, Shuichi Samata, Masanori Numano, Hiroyuki Fukui
  • Patent number: 5271796
    Abstract: A method of detecting a defect on the surface of a semiconductor substrate, including: a first etching step of etching a semiconductor substrate by a first etching amount; a first check step of applying a beam to the surface of the substrate underwent the first etching step, and detecting a first reflected beam; a second etching step of etching the substrate etched by the first etching amount, by an additional etching amount, to make the total etching amount a second etching amount; a second check step of applying the beam to the surface of the substrate underwent the second etching step, and detecting a second reflected beam; and a calculation step of calculating the relation between the first and second reflected beams.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: December 21, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Mokuji Kageyama, Hachiro Hiratsuka
  • Patent number: 5071776
    Abstract: First, silicon wafers are formed by cutting silicon monocrystalline ingot into slices. Then back side and main surfaces of the wafers are subjected to lapping and etching processes. Next, the wafers are submerged into substantially pure water and ultrasonic waves are applied to the wafer surface via the water to clean at least one of the surfaces of each of the wafers and form gettering damage on the wafer surface. After this, the main surfaces of the wafers which have been subjected to the cleaning and damage-forming process and on which semiconductor elements are to be formed are polished into mirror finish.
    Type: Grant
    Filed: November 25, 1988
    Date of Patent: December 10, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Matsushita, Moriya Miyashita, Makiko Wakatsuki, Norihiko Tsuchiya, Atsuko Kubota
  • Patent number: 4980300
    Abstract: When a surface of semiconductor wafer is treated for gettering, ultrasonic waves are caused to propagate along the surface of the semiconductor wafer, through pure water. Mechanical damages are formed on the surface of the semiconductor wafer along which the ultrasonic waves propagated, the damages serving as a back side damage.
    Type: Grant
    Filed: November 25, 1988
    Date of Patent: December 25, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Shintaro Yoshii, Keiko Sakuma
  • Patent number: 4971920
    Abstract: An ultrasonic wave is propagated to the surface of a semiconductor wafer in pure water to effect the gettering treatment with respect to the surface of the semiconductor wafer. Mechanical damages are formed on the surface of the semiconductor wafer to which the ultrasonic wave is applied, and at the same time the surface of the semiconductor wafer is cleaned. The mechanical damages serve to function as back side damage.
    Type: Grant
    Filed: November 25, 1988
    Date of Patent: November 20, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Moriya Miyashita, Ayako Maeda