Abstract: A method of manufacturing wiring layers of semiconductor devices in which a base layer made of electroconductive material is formed on a wiring-intended area of the substrate surface and an insulating layer is formed on the area other than the wiring intended area. Then the wiring layer is grown on the base layer up to substantially the same level as that of the insulating layer up, hereby planarity of the surfaces of the device is maintained after wiring formation.

Abstract: A method of manufacturing a CMOS semiconductor device includes the step of preparing a substrate having a first region of a second conductivity type serving as prospective source and drain formation regions of a transistor of a first conductivity type, and a second region of the first conductivity type serving as a prospective channel formation region of a transistor of the second conductivity type. The method of manufacturing the device further includes the steps of simultaneously doping an impurity of the first conductivity type having a first concentration in a first depth of each of the first and second regions, and doping an impurity of the first conductivity type having a concentration higher than the first concentration in a second depth smaller than the first depth of the first region.

Abstract: A semiconductor device comprises a semiconductor substrate of first conductivity type with a major surface having an element isolation region formed on it.

Abstract: A method of manufacturing a semiconductor device has the steps of forming an insulating film on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, converting either all of the polycrystalline silicon layer or a portion of predetermined thickness of the polycrystalline silicon layer into an amorphous silicon layer, patterning the polycrystalline silicon layer, either all of which or a portion of predetermined thickness of which has been converted into an amorphous silicon layer, and ion-implanting an impurity in the semiconductor substrate using the patterned layer as a mask.

Abstract: A polycrystalline silicon layer is formed on a surface of a gate oxide film on a silicon substrate. A mask is formed on a prospective gate region of the polycrystalline silicon layer. Nitrogen is ion-implanted using the mask into a portion of the polycrystalline silicon layer excluding the prospective gate region. In addition, an impurity for forming source and drain regions is ion-implanted into portions of the substrate. The ion-implanted nitrogen is then annealed to convert the portion of the substrate in which nitrogen has been ion-implanted into an electrically insulating layer. The portion in which no nitrogen has been ion-implanted functions as a gate electrode. An upper portion of the polycrystalline silicon layer is etched using the mask before the nitrogen is annealed. Thus, the upper surfaces of the insulating layer and the gate electrode can be level with each other after annealing.