Abstract: An EEPROM enabling high density integration with less power consumption includes source/drain regions formed on the main surface of a P type silicon substrate, and a pair of memory transistors formed therebetween, and a selecting transistor formed between memory transistors and on the main surface of the P type semiconductor substrate. Memory transistors include control gates, and floating gates, respectively. Writing and erasure of data are conducted taking advantage of F-N tunnel phenomenon through tunnel regions.

Abstract: An improved NAND type EEPROM is disclosed, in which one selecting transistor and a plurality of memory transistors constituting one memory block are connected in series, a tunnel region for writing/erasing signal charges is isolated from a read transistor region for reading presence/absence of stored charge in each of the memory transistors. The plurality of memory transistors share one selecting transistor and the read transistor region and the selecting transistor region are isolated from each other, so that the memory block can be made small and the threshold values of the plurality of memory transistors are not influenced by the number of the memory transistors.