Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is transmitted to the second device.

Abstract: Methods and systems for optimizing an application include optimizing, with a processor on a first device, an application for a second device in accordance with an application execution profile received from the second device to generate a binary for the application that is optimized for use indicated by the application execution profile. The optimized binary is transmitted to the second device.

Abstract: A thread priority control mechanism is provided which uses the completion event of the preceding transaction to raise the priority of the next transaction in the order of execution when the transaction status has been changed from speculative to non-speculative. In one aspect of the present invention, a thread-level speculation mechanism is provided which has content-addressable memory, an address register and a comparator for recording transaction footprints, and a control logic circuit for supporting memory synchronization instructions. This supports hardware transaction memory in detecting transaction conflicts. This thread-level speculation mechanism includes a priority up bit for recording an attribute operand in a memory synchronization instruction, a means for generating a priority up event when a thread wake-up event has occurred and the priority up bit is 1, and a means for preventing the CAM from storing the load/store address when the instruction is a non-transaction instruction.

Abstract: A thread priority control mechanism is provided which uses the completion event of the preceding transaction to raise the priority of the next transaction in the order of execution when the transaction status has been changed from speculative to non-speculative. In one aspect of the present invention, a thread-level speculation mechanism is provided which has content-addressable memory, an address register and a comparator for recording transaction footprints, and a control logic circuit for supporting memory synchronization instructions. This supports hardware transaction memory in detecting transaction conflicts. This thread-level speculation mechanism includes a priority up bit for recording an attribute operand in a memory synchronization instruction, a means for generating a priority up event when a thread wake-up event has occurred and the priority up bit is 1, and a means for preventing the CAM from storing the load/store address when the instruction is a non-transaction instruction.

Abstract: A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge OR operations.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: A thread priority control mechanism is provided which uses the completion event of the preceding transaction to raise the priority of the next transaction in the order of execution when the transaction status has been changed from speculative to non-speculative. In one aspect of the present invention, a thread-level speculation mechanism is provided which has content-addressable memory, an address register and a comparator for recording transaction footprints, and a control logic circuit for supporting memory synchronization instructions. This supports hardware transaction memory in detecting transaction conflicts. This thread-level speculation mechanism includes a priority up bit for recording an attribute operand in a memory synchronization instruction, a means for generating a priority up event when a thread wake-up event has occurred and the priority up bit is 1, and a means for preventing the CAM from storing the load/store address when the instruction is a non-transaction instruction.

Abstract: A converter for converting an application program that is executed for every job request into a batch processing program for collectively processing a plurality of job requests. The converter includes: a code identifier for identifying a portion of the application program that includes a service request to another server, and a portion that does not include a service request; an integration unit for converting the service request into a collective service request that collectively issues a plurality of service requests corresponding to the plurality of job requests; a multiplexing unit for converting the processing code in the application program into a multiplexed code for executing multiple processings corresponding to the plurality of job requests; and an output unit for outputting, as the batch processing program, the application program that the integration unit and the multiplexing unit have processed.

Abstract: A computer-implemented method, apparatus, and computer program-product for controlling cache. The method includes the steps of assigning a value corresponding to a transaction to a memory object that is created while a computer application is processing the transaction; adding the assigned value as a transaction flag value to a flag area of a cache array in accordance with the storage of the memory object in the cache; registering the corresponding transaction flag value as a victim candidate at the completion of the transaction; and in response to eviction of a cache line, preferentially evicting a cache line having the transaction flag value registered as the victim candidate.

Abstract: A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge OR operations.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the streams of data include Merge AND and Merge OR operations.

Abstract: An image display system comprises: a transmission device (PC), for transmitting image data upon receiving a drawing command from an OS or an application; and a receiving monitor, for displaying, on a high-resolution panel, image data received via a monitor cable, wherein the transmission device includes a drawing command analysis device, for detecting an area on a screen wherein the content is changed by the drawing command, and for employing the detected area to calculate an area to be transmitted, and a graphics card, for transmitting a packet that includes the calculated area to be transmitted, and control data provided as header data for the area to be transmitted, and wherein the receiving monitor includes a packet reception device, for analyzing the header data in the received packet and for, based on the header data, rendering image data in an internally provided frame memory.

Abstract: A converter for converting an application program that is executed for every job request into a batch processing program for collectively processing a plurality of job requests. The converter includes: a code identifier for identifying a portion of the application program that includes a service request to another server, and a portion that does not include a service request; an integration unit for converting the service request into a collective service request that collectively issues a plurality of service requests corresponding to the plurality of job requests; a multiplexing unit for converting the processing code in the application program into a multiplexed code for executing multiple processings corresponding to the plurality of job requests; and an output unit for outputting, as the batch processing program, the application program that the integration unit and the multiplexing unit have processed.

Abstract: An image display system comprises: a transmission device (PC) 10, for transmitting image data upon receiving a drawing command from an OS or an application; and a receiving monitor 40, for displaying, on a high-resolution panel 41, image data received via a monitor cable 39, wherein the transmission device 10 includes a drawing command analysis device 20, for detecting an area on a screen wherein the content is changed by the drawing command, and for employing the detected area to calculate an area to be transmitted, and a graphics card 12, for transmitting a packet that includes the calculated area to be transmitted, and control data provided as header data for the area to be transmitted, and wherein the receiving monitor 40 includes a packet reception device 50, for analyzing the header data in the received packet and for, based on the header data, rendering image data in an internally provided frame memory.

Abstract: A converter for converting an application program that is executed for every job request into a batch processing program for collectively processing a plurality of job requests. The converter includes: a code identifier for identifying a portion of the application program that includes a service request to another server, and a portion that does not include a service request; an integration unit for converting the service request into a collective service request that collectively issues a plurality of service requests corresponding to the plurality of job requests; a multiplexing unit for converting the processing code in the application program into a multiplexed code for executing multiple processings corresponding to the plurality of job requests; and an output unit for outputting, as the batch processing program, the application program that the integration unit and the multiplexing unit have processed.

Abstract: An embodiment of the present inventions is a method for encoding/decoding data of variable length format and is used to omit unnecessary pieces of data for the purpose of improving processing performance, reducing the size of data on communication paths and efficiently using limited physical memory. As examples of such variable length encoding, BER compression and UTF-8 encoding of UNICODE text, etc., are cited. While the amount of data can be reduced through encoding, before the data is actually used, it is necessary to restore (decode) it to the original data, which requires a great deal of processing time. One aspect of the present invention is improving decoding by reducing the processing time required to decode the encoded data.

Abstract: A computer-implemented method, apparatus, and computer program-product for controlling cache. The method includes the steps of assigning a value corresponding to a transaction to a memory object that is created while a computer application is processing the transaction; adding the assigned value as a transaction flag value to a flag area of a cache array in accordance with the storage of the memory object in the cache; registering the corresponding transaction flag value as a victim candidate at the completion of the transaction; and in response to eviction of a cache line, preferentially evicting a cache line having the transaction flag value registered as the victim candidate.