Patents by Inventor Moriyuki Takamura

Moriyuki Takamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiprocessor system and parallel processing method for processing data transferred between processors
    Patent number: 5896501
    Abstract: A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: April 20, 1999
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ikeda, Shigeru Nagasawa, Haruhiko Ueno, Naoki Shinjo, Teruo Utsumi, Kazushige Kobayakawa, Naoki Sueyasu, Kenichi Ishizaka, Masami Dewa, Moriyuki Takamura
  • Synchronous processing method and apparatus for a plurality of processors executing a plurality of programs in parallel
    Patent number: 5634071
    Abstract: A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: May 27, 1997
    Assignee: Fujitsu Limited
    Inventors: Masami Dewa, Shigeru Nagasawa, Masayuki Ikeda, Haruhiko Ueno, Naoki Shinjo, Teruo Utsumi, Kazushige Kobayakawa, Kenichi Ishizaka, Moriyuki Takamura
  • Error correcting and detecting system
    Patent number: 4631725
    Abstract: An error correcting and detecting system using a parity check H-matrix divided into a plurality of block vectors each including four or three column vectors each having eight elements. In the H-matrix, (i) there are no all "0" vectors; (ii) all column vectors are different from each other; (iii) 8 column vectors each having only one "1" is included therein, (iv) each column vector has an odd number of "1's"; (v) the modulo-2 sum of any three column vectors within any block never equals any column vectors of the H-matrix; (vi) the modulo-2 sum of four column vectors within any block never equals an all "0" vector; and (vii) the modulo-2 sum of eight column vectors within any two blocks never equals an all "0" vector.
    Type: Grant
    Filed: December 27, 1984
    Date of Patent: December 23, 1986
    Assignee: Fujitsu Limited
    Inventors: Moriyuki Takamura, Shigeru Mukasa, Takashi Ibi