Abstract: An error reduction circuit for use in arrays of chalcogenide memory and computing devices. The error reduction circuit reduces the error associated with the output response of chalcogenide devices. In a preferred embodiment, the output response is resistance and the error reduction circuit reduces errors or fluctuations in the resistance. The error reduction circuit includes a network of chalcogenide devices, each of which is nominally equivalent and each of which is programmed into the same state having the same nominal resistance. The inclusion of multiple devices in the network of the instant error reduction circuit provides for a reduction in the contributions of both dynamic fluctuations and manufacturing fluctuations to the error in the output response.