Abstract: A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) to accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).

Abstract: A First In First Out shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A read address ring counter (36) and write address ring counter (32) are responsive to respective read and write pulses to sequentially perform memory read and write operations. A comparator (40) compares the address outputs of the ring counters (36, 32) for equality. A read and a write signal generator (80, 60) are provided for producing respective read and write pulses in response to input transitions of read and write commands. A last operation R/W flip-flop (70) maintains an account of the last read and write memory operation processed by the system.

Abstract: A sequential memory (10) includes synchronous write control circuitry (26) and synchronous read control circuitry (22). The synchronous write control circuitry produces an Input Ready (IR) signal synchronous with the WRTCLK signal. The synchronous read control circuitry (22) generates a Output Ready (OR) signal synchronously with the RDCLK signal. A RSAM (read sense amplifier) signal is provided to read the sense amplifier associated with a memory (12) responsive to the RDCLK if a RAMRDY signal indicates that a read from this location may be requested on the next clock cycle.

Abstract: A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written to and read from. Output buffer circuits (22a-b) allow a data word to be read instantaneously after it is written to the sequential memory (10).

Abstract: A data access controller (10) is comprised of a control circuit (12) and an output data latch (14). The control circuit (12) receives a READ and WRITE signal (30,32) and produces a plurality of control signals (22). The output data latch (14) allows either incoming data (24) or data from a memory (16) to be propagated to the output for data access depending on the state of the control signals. The data access controller (10) enables faster data access of first in, first out memory structures.

Abstract: A FIFO 12 has a status flag generator 14. The status flag generator 14 includes a register programmable to "N". It also includes two sets of gray-code counters and a register (22,23,21;26,25,24) that are driven by separate READ and WRITE CLKS. The registers and counters are connected to comparators (31-36) for generating a plurality of signals that are input to output latches (41-43). The status flag generator is capable of generating status signals of FULL, HALF-FULL, EMPTY, FULL-N and EMPTY+N. N is a user-defined number that is programmed into a register 20 that is selectively connected to one or more of the programmable gray-code counters (23,24).

Abstract: A first-in, first-out memory has a write pointer (34) that includes a higher-order ring counter (192) and a lower-order ring counter (190). Ring counters (190, 192) store respective higher-order and lower-order address digits that are together used to select one of a plurality of write select gates (202). Each gate (202) is operable to both power up and address is coupled to a respective memory word location. A read pointer (28) of the FIFO has an analogous architecture. The lower-order and higher-order address digits generated by the write and read pointers (34 and 28) are used by a pointer comparator (44) to generate a plurality of intermediate signals. The intermediate signals are in turn received by a flag decoder (52) that generates EMPTY, FULL, ALMOST-FULL/EMPTY, and HALF-FULL status flags. A write-read control section (48) of the FIFO has a pair of monostable multivibrators (68, 82) that generate write and read clock pulses of a uniform pulse width.

Abstract: A cascadable first-in, first-out memory unit (11, 12, 13) has a load/unload control (152) for write-addressing and read-addressing selected memory locations within its memory array (82). A write pointer (110, 112, 120) keeps track of the number of write operations that have occurred in the selected memory unit, and a read pointer (130, 132, 142) does the same for the number of read operations. When the number of write operations performed since a last reset pulse (416) equals the number of memory locations in the memory array (82), write control passes to the next succeeding FIFO memory unit by a descending transition of an output control signal (444). Read control is passed to the subsequent FIFO by an ascending transition (470) of the same output control signal.

Abstract: A First-In First-Out (FIFO) shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A write address ring counter (32) is responsive to first transitions (164, 168) of a write pulses to increment to successive stages (32) therein. A plurality of latches (154) are each responsive to a second transition (166) to latch in a write address bit. The latches (154) are each enabled to write the address bit to a respective memory register (50) upon a successive first transition (168).