Abstract: A method and apparatus for video motion compensation, power of two reduction and color format conversion is disclosed. The motion compensation engine performs the MPEG-2 functions of half pel compensation, inverse discrete cosine transform and merge. Dual prime, field-based and frame-based macroblocks are supported. Data reduction may be performed in the vertical direction, the horizontal direction, or both.

Abstract: A method and apparatus for horizontally expanding a video graphics adapter (VGA) text character display image to fully fill the screen of a flat panel display. Cell lines for each character are remapped to provide expanded cell lines. The flat panel apparatus includes a video memory for storing the character code, attribute data and font data, a character generator for generating character font data based on the character code, a lookup table for providing expanded cell lines, and an attribute controller for combining the font data and the attribute data for output to a flat panel display.

Abstract: An apparatus for scalable image processing includes a display, multiple graphics functional units and a mode selector. Each of the graphics functional units has a configuration of a predetermined type to control the display. The mode selector determines which combination of graphics functional units controls the display. A method for scalable image processing includes monitoring at least one parameter, determining whether to switch from one graphics functional unit configuration to a new graphics functional unit configuration based upon one or more of the parameters, and switching to the new graphics functional unit configuration.

Abstract: An apparatus for scalable image processing includes a display, multiple graphics functional units and a mode selector. Each of the graphics functional units has a configuration of a predetermined type to control the display. The mode selector determines which combination of graphics functional units controls the display. A method for scalable image processing includes monitoring at least one parameter, determining whether to switch from one graphics functional unit configuration to a new graphics functional unit configuration based upon one or more of the parameters, and switching to the new graphics functional unit configuration.

Abstract: A method and apparatus for horizontally expanding a video graphics adapter (VGA) text character display image to fully fill the screen of a flat panel display. Cell lines for each character are remapped to provide expanded cell lines. The flat panel apparatus includes a video memory for storing the character code, attribute data and font data, a character generator for generating character font data based on the character code, a lookup table for providing expanded cell lines, and an attribute controller for combining the font data and the attribute data for output to a flat panel display.

Abstract: A method and apparatus for video motion compensation, power of two reduction and color format conversion is disclosed. The motion compensation engine performs the MPEG-2 functions of half pel compensation, inverse discrete cosine transform and merge. Dual prime, field-based and frame-based macroblocks are supported. Data reduction may be performed in the vertical direction, the horizontal direction, or both.

Abstract: A memory architecture for a video graphics controller includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and a bus. The DRAM includes a data port, an address decoder that can receive an address to select a memory location in the DRAM and a command instruction bus that can receive instructions for data transfer. The SRAM includes a first data port to transfer data with the DRAM, a second data port to transfer data with other than the DRAM, a first address decoder that can receive an address to select a memory location in the SRAM for data transfer with the DRAM, a first read/write input that can receive a signal for data transfer with the DRAM, a second address decoder that can receive an address to select a memory location in a page of the SRAM to transfer data with other than the DRAM and a second read/write input that can receive a signal for data transfer from other than the DRAM.

Abstract: The invention is an improved method and apparatus for implementing the “least-recently-used” (LRU) replacement algorithm in a memory. A counter keeps count of the number of memory accesses. Each block in the memory is associated with a time tag that represents an approximation of the age in the memory. The criteria for updating a time tag is based upon the value of the counter and the time tag. The block with a time tag value representing the highest residence time in memory with respect to the other time tags is always replaced first. The time tag for the most recently accessed block is set to a value representing the least residence time in memory and the other time tags are updated based upon their age in the memory.

Abstract: A method and apparatus for horizontally expanding a video graphics adapter (VGA) text character display image to fully fill the screen of a fiat panel display. Cell lines for each character are remapped to provide expanded cell lines. The flat panel apparatus includes a video memory for storing the character code, attribute data and font data, a character generator for generating character font data based on the character code, a lookup table for providing expanded cell lines, and an attribute controller for combining the font data and the attribute data for output to a flat panel display.

Abstract: A system for performing input and output operations to and from a processor in which interrupts for I/O operations are conditionally generated internally rather than externally by (Super State.TM.) microcode residing in a separate address space in memory in an area protected from the user. A (superblock) register in the processor points to the Super State area in memory. If the Super State mode is turned on, an interrupt is generated within the processor whenever the control table allows. The interrupt directs the processor to the register and hence to the Super State code. By way of example, the Super State code controls power and access to the port, decides whether to put the interrupt in memory and emulate the I/O, and counts access to the port. The invention provides a processor with the flexibility of performing I/O operations to and from memory and/or to a peripheral or to trap an interrupt into a new operating environment for device emulation.

Abstract: The present invention includes a memory clock system for a graphics controller including a plurality of clock pulse generators, and a clock controller which selects the clock frequency based on the state of the graphics controller functional units.

Abstract: A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time periods when data is being repeated, thus increasing display memory bandwidth. Display data from a location in display memory is stored in a latch, and is output from the latch until the tag information indicates no more data repetitions occur.

Abstract: An efficient organization for microcoded instruction sets which have processor operations in which not all the bits of an instruction word are required. The organization has two registers for receiving and holding the first and second byte of instructions at a time, a first ROM connected to the register for decoding the first byte into control signals for operation of said microprocessor. One of these control signals is generated whenever the portion of the second instruction byte is required. The organization also has a second ROM connected to the register for decoding the portion of the second byte into control signals. Connected to said first and second ROMs is a multiplexer which selects the decoded second byte control signals for operation of the microprocessor responsive to the first ROM control signal.

Abstract: A instruction fetch circuit which allows portions of the instruction to be decoded and executed independently. The invention includes a first register for storing a digital data word having first and second bytes. The first register provides first and second outputs of the first and second digital bytes respectively. A first multiplexer circuit is included for selecting and storing either of the first or second outputs of the first register and providing a first intermediate output corresponding thereto. A second multiplexer circuit is included for selecting and storing either of the first or second outputs of the first register or the first intermediate output of the first multiplexer circuit and providing a second intermediate output corresponding thereto. Control circuitry is included for selectively activating the first register and the first and second multiplexer circuits to present portions of the instruction for decoding. Additional multiplexer circuits are included to handle larger instructions.

Abstract: An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU. The ALU provides a variety of arithmetic and logic functions for application to 24-bit operands, but also includes a capability of manipulating such operands in accordance with sign extended opcodes without actually physically executing a sign extend operation within the microprocessor. In this manner, the ALU executes the necessary logic functions to provide the same ultimate result as sign bit extension, but does not require a separate sign bit extension step within the microprocessor to convert signed byte operand into a signed word operand.

Abstract: Display control logic for a terminal controller with support for such features as windows and interlace. A display list processor (DLP) (20) communicates with a program memory (12) containing DLP instructions, a display memory (12) containing character codes and attributes for the display, and a font memory (13). As the DLP program executes, it causes accesses to the display memory and brings in character codes and attributes for ultimate display on the screen. These character codes and attributes, as well as information representative of the scan line are input to a video data queue (95). The queue entries are clocked out of the queue by a character clock (170) and are used to generate addresses to font memory. Bitmaps from font memory are read into a dot shifter (190). The DLP instruction set includes a DISPLAY STRING instruction which allows a portion of a scan line to be built up by specifying the length of the scan line segment and the starting address in memory.

Abstract: An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU. The ALU provides a variety of arithmetic and logic functions for application to 24-bit operands, but also includes a capability of manipulating such operands in accordance with sign extended opcodes without actually physically executing a sign extend operation within the microprocessor. In this manner, the ALU executes the necessary logic functions to provide the same ultimate result as sign bit extension, but does not require a separate sign bit extension step within the microprocessor to convert signed byte operand into a signed word operand.