Abstract: An impedance is connected by a switching circuit, to sense/inhibit windings of a core memory at the end of each memory cycle. The result is an effectively decreased time constant for the core windings which permits faster memory operation. The circuit further reverse biases diodes connected to the input terminals of a sense amplifier during a read cycle thereby increasing the isolation of this amplifier from the effects of inhibit current pulses occurring during a memory read cycle.

Abstract: A densely packed low weight, low volume, minimum temperature gradient memory array comprising a bilateral printed circuit board having a plurality of ferrite cores arranged in columns and rows mounted on one side and a plurality of integrated circuit diode flatpacks mounted on the other side. A ground plane comprising a thin metallic layer isolates the core plane from the mounting and also serves as a means for maintaining a minimum temperature gradient across the core plane. A heat conductor removes unwanted heat from the array, and the connections to elements of the array are grouped to reduce wiring runs.