Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm?2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm?2 or less, or 100 cm?2 or less, or 10 cm?2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm?2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm?2 or less, or 100 cm?2 or less, or 10 cm?2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Abstract: Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm?2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm?2 or less, or 100 cm?2 or less, or 10 cm?2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Abstract: Methods and systems for low etch pit density gallium arsenide crystals with boron dopant may include a gallium arsenide single crystal wafer having boron as a dopant, an etch pit density of less than 500 cm?2, and optical absorption of 6 cm?1 or less at 940 nm. The wafer may have an etch pit density of less than 200 cm?2. The wafer may have a diameter of 6 inches or greater. The wafer may have a boron concentration between 1×1019 cm?3 and 2×1019 cm?3. The wafer may have a thickness of 300 ?m or greater. Optoelectronic devices may be formed on a first surface of the wafer, which may be diced into a plurality of die and optical signals from an optoelectronic device on one side of one of the die may be communicated out a second side of the die opposite to the one side.

Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.

Abstract: A IIIA-VA group semi-conductor single crystal substrate (2) has one of or both of the following two properties: an oxygen content of 1.6×1016-5.6×1017 atoms/cm3 in a range from the surface to a depth of 10 ?m of the wafer, and an electron mobility of 4,800 cm2/V·s-5,850 cm2/V·s. Further, a method for preparing the semi-conductor single crystal substrate (2) comprises: placing a single crystal substrate (2) to be processed in a container (4); sealing said container (4), and keeping said single crystal substrate (2) to be processed at a temperature in the range of from the crystalline melting point ?240° C. to the crystalline melting point ?30° C. for 5 hours to 20 hours; preferably, keeping a gallium arsenide single crystal at a temperature of 1,000° C. to 1,200° C. for 5 hours to 20 hours.

Abstract: A method of controlling oxygen concentration in III-V compound semiconductor substrate comprises providing a plurality of III-V crystal substrates in a container, providing a predetermined amount of material in the container. Atoms of the predetermined amount of material having a high chemical reactivity with oxygen atoms. The method further comprises maintaining a predetermined pressure within the container and annealing the plurality of III-V crystal substrates to yield an oxygen concentration in the crystal substrates. The oxygen concentration is associated with the predetermined amount of material.

Abstract: An IIIA-VA group semi-conductor single crystal substrate (2) has one of or both of the following two properties: the content of oxygen in the range from the surface of the wafer to a depth of 10 ?m ranges from 1.6×1016 atoms/cm3 to 5.6×1017 atoms/cm3, and an electron mobility ranges from 4,800 cm2/V·S to 5,850 cm2/V·S. Further, a method for preparing the semi-conductor single crystal substrate (2) comprises: placing a to-be-processed single crystal substrate (2) in a container (4); sealing the container (4), and keeping the to-be-processed single crystal substrate (2) in a temperature range in which the crystalline melting point is from ?240° C. to ?30° C. for 5 hours to 20 hours; preferably, keeping a gallium arsenide single crystal at a temperature of 1,000° C. to 1,200° C. for 5 hours to 20 hours.

Abstract: An electronic device for analysis of a body fluid comprises a housing defining an opening therein, a measuring facility and at least one electrical circuit arranged inside the housing, and a multi-wire connector carried by the housing. The measuring facility is configured to receive a test element therein via the opening and to produce measuring values relating to a sample of the body fluid received on the test element. The at least one electrical circuit is configured to process the measuring values to yield analytical data corresponding to a component of the sample of the body fluid. The multi-wire connector has at least one wire defining a voltage supply input to the electronic device, and is configured to be connected to a mating connector of an external electronic device with the at least one wire configured to receive a supply voltage from the external electronic device.

Abstract: An apparatus and method of treating multiple wafers to reduce the density of impurities as well as to improve the uniformity of substrate electrical characteristics without any thermal stress. The wafers are chemically treated, and heat treated in a sealed reaction tube under arsenic overpressure with a controlled thermal profile to heat the wafers. The thermal profile controls temperature of different zones inside of a furnace containing the sealed reaction tube. Impurities of the wafers are dissolved, and are out-diffused from the inner portions to the outer portions of the wafers.

Abstract: Systems, client computing devices, server computing devices, and methods are disclosed for accessing medical devices, providing remote access to medical devices and/or remotely accessing medical devices. In one exemplary embodiment, client computing devices utilize protocol components that may be obtained from a server computing device via a network to communicate with medical devices in a communications protocol supported by the medical device.

Abstract: An apparatus and a method for growth of Group III-V monocrystalline semiconductor compounds in a closed system with a balanced pressure maintained between the inside of a sealed ampoule and a pressure vessel. The vapor pressure inside the sealed ampoule can be controlled by temperature, the amount of polycrystalline charge and an amount of material such as phosphorus inside the sealed ampoule. Filling and release of an inert gas is used to control the pressure in the pressure vessel.

Abstract: An apparatus and method of treating multiple wafers to reduce the density of impurities as well as to improve the uniformity of substrate electrical characteristics without any thermal stress. The wafers are chemically treated, and heat treated in a sealed reaction tube under arsenic overpressure with a controlled thermal profile to heat the wafers. The thermal profile controls temperature of different zones inside of a furnace containing the sealed reaction tube. Impurities of the wafers are dissolved, and are out-diffused from the inner portions to the outer portions of the wafers.