Abstract: A method for debugging network activity involving receiving, by HCA, a packet stream comprising multiple packets, comparing a packet header of each of the packets to a trigger condition to determine whether the trigger condition has been met, after the trigger condition has been met, comparing each packet header of the packets to one or more trace filters stored in the HCA to identify matching packets, duplicating one or more portions of the matching packets and storing the duplicated portions of the matching packets in a trace buffer, where the trace buffer is located in the HCA and is dynamically repurposed from a payload RAM to the trace buffer when a corresponding port of the HCA for transmitting or receiving the packet stream is set to trace mode, and stopping the trace and copying the one or more portions of packets from the trace buffer to host memory.

Abstract: A method for content addressable memory (CAM) error recovery that includes detecting an error in an entry of a CAM, identifying an address of the entry in the CAM, copying data from the address in the backup random access memory (RAM) into the entry of the CAM to obtain a corrected CAM, clearing a results (first in first out) FIFO structure based on detecting the error, performing, using the corrected CAM, a match request stored in a replay FIFO structure to obtain a revised result, and storing the revised result in the results FIFO structure.

Abstract: An Infiniband port can be provided. The port can have an input buffer for storing received data, a flow control manager operable to detect an available space in the input buffer, and a packet generator operable to generate a flow control packet to advertise available space in the input buffer to a remote device transmitting data for storage in the input buffer. The flow control manager can be operable to trigger the packet generator to generate a flow control packet on the basis of at least one of a timer, a received data quantity characteristic for the input buffer and a buffer utilization characteristic for the input buffer.

Abstract: A method for multicast replication by a host channel adapter (HCA) involving receiving a multicast packet, by a receive pipeline for processing packets of the HCA, storing, in a payload RAM within the HCA, a multicast packet payload corresponding to a data portion of the multicast packet, identifying, from a multicast header of the multicast packet, a plurality of destination underlying functions and a plurality of corresponding destination QPs to which the multicast packet is directed, wherein each destination underlying function of corresponds to a virtual machine located on a host, identifying, from the multicast header, information to be replicated for each multicast packet destination, injecting, by the HCA, a number of multicast packet descriptors corresponding to a number of the corresponding destination QPs into the receive pipeline of the HCA, and copying, from the payload RAM, the multicast packet payload to each of the corresponding destination QPs.

Abstract: A method for content addressable memory (CAM) error recovery that includes detecting an error in an entry of a CAM, identifying an address of the entry in the CAM, copying data from the address in the backup random access memory (RAM) into the entry of the CAM to obtain a corrected CAM, clearing a results (first in first out) FIFO structure based on detecting the error, performing, using the corrected CAM, a match request stored in a replay FIFO structure to obtain a revised result, and storing the revised result in the results FIFO structure.

Abstract: A method for debugging network activity involving receiving, by HCA, a packet stream comprising multiple packets, comparing a packet header of each of the packets to a trigger condition to determine whether the trigger condition has been met, after the trigger condition has been met, comparing each packet header of the packets to one or more trace filters stored in the HCA to identify matching packets, duplicating one or more portions of the matching packets and storing the duplicated portions of the matching packets in a trace buffer, where the trace buffer is located in the HCA and is dynamically repurposed from a payload RAM to the trace buffer when a corresponding port of the HCA for transmitting or receiving the packet stream is set to trace mode, and stopping the trace and copying the one or more portions of packets from the trace buffer to host memory.

Abstract: A method for multicast replication by a host channel adapter (HCA) involving receiving a multicast packet, by a receive pipeline for processing packets of the HCA, storing, in a payload RAM within the HCA, a multicast packet payload corresponding to a data portion of the multicast packet, identifying, from a multicast header of the multicast packet, a plurality of destination underlying functions and a plurality of corresponding destination QPs to which the multicast packet is directed, wherein each destination underlying function of corresponds to a virtual machine located on a host, identifying, from the multicast header, information to be replicated for each multicast packet destination, injecting, by the HCA, a number of multicast packet descriptors corresponding to a number of the corresponding destination QPs into the receive pipeline of the HCA, and copying, from the payload RAM, the multicast packet payload to each of the corresponding destination QPs.

Abstract: One embodiment of the invention provides a method of operating a switch in a communications network. The method includes storing a set of routings for each port in the switch. When a packet is received at a port in the switch, the set of routings corresponding to the port at which the packet was received is accessed. A port from which to forward the packet from the switch is determined in accordance with the set of routings. The packet is then duly forwarded over the network from the port as determined by the routings.

Abstract: There is described an apparatus and method for implementing a communications port. The apparatus comprises a core, which is operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing. Each sub-port is allocated a corresponding data transfer capacity.

Abstract: An Infiniband switch can have an input port and a plurality of output ports. The switch can be configured to interrogate at least a header portion of a received packet to determine an output port for the packet and to forward the packet to an output buffer associated with the determined output port. The switch can also be configured to determine an output buffer ratio in dependence upon at least an inbound data rate characteristic of the input port and an outbound data rate characteristic of the determined output port. The output port can be configured to commence onward transmission of the packet once a proportion of the packet conforming to the output buffer ratio has been written into the output buffer.

Abstract: One embodiment of the invention provides a method of operating a switch with cut-through routing in a communications network. The method includes receiving a packet at a first port of the switch and determining a second port of the switch from which the received packet is to be forwarded out over the network. At least one authentication check is performed on the received packet. In general, the switch starts to forward the received packet from the second port prior to complete reception of the packet at the first port. However, this onward transmission is delayed until the authentication check has completed. This ensure that none of the received packet is forwarded from the second port if any authentication check fails.

Abstract: There can be provided a port operable for a PCI Express link. The port can comprise a scheduler operable to determine a next management packet transmission time, and a windower operable to determine a transmission window based upon the next management packet transmission time. The port can also comprise an inserter operable to examine a data packet stream to determine whether a gap therein occurs during the transmission window, and if such a gap does occur to control insertion of a management packet thereinto. Thus transmission efficiency for management packets over the link can be increased.

Abstract: An Infiniband switch can be provided. The switch can have an input port logic unit for determining an output virtual lane for a received packet and for storing a descriptor of the determined output virtual lane in a packet field not protected by a checksum field of the packet. The switch can also have a routing unit for transferring the received packet to an output port corresponding to the determined output virtual lane. Additionally, the switch can have an output port logic unit for simultaneously checking the integrity of the packet transferred through the routing unit and calculating a new value for the checksum with the descriptor moved to a correct packet field, which field is included in the calculation of the checksum.

Abstract: An Infiniband device is provided. The device has a plurality of input/output ports. Each port has associated therewith an input buffer for storage of a packet received at that port. Each port also has associated therewith a plurality of output buffers for storage of a packet transmitted from an input buffer via a switching matrix. Each port is arranged to share its associated plurality of output ports with at least one other port. Each input buffer is also associated with a single output buffer of each shared plurality of output buffers. A packet received at an input buffer is transmitted to all associated output buffers via the switching matrix in parallel with an output buffer select signal. The output buffer select signal is sent to less than all of the associated output buffers, any output buffer not receiving the output buffer select signal is configured to discard the packet transmitted from the input buffer.

Abstract: An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequence to a destination. The control logic can further be operable on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet.

Abstract: A receiver for digital data is provided. The receiver comprises a ring buffer operable to store received data. The receiver also comprises a write pointer controller for the buffer, operable to control the writing of received data into the buffer, and a read pointer controller for the buffer, operable to control the reading of data from the buffer. The receiver further comprises a pointer adjustment controller operable, in response to a detection of a special data indicator, to control at least one of the write pointer controller and the read pointer controller using forward looking operable to foresee a data location within the buffer corresponding to a future read location of the buffer.

Abstract: An interconnect apparatus includes a transaction packet buffer and control logic. The control logic can be operable sequentially to write transaction packets for transmission to the transaction packet buffer and to transmit the buffered transaction packets in sequence to a destination. The control logic can further be operable on receipt of a control packet indicative of non-receipt by the destination of a transmitted transaction packet to retransmit the non-received transaction packet and transaction packets transmitted from the transaction packet buffer subsequent to the non-received transaction packet.

Abstract: There is described an apparatus and method for implementing a communications port. The apparatus comprises a core, which is operable to divide the port into a plurality of sub-ports by dividing a data transfer capacity of the port among the plurality of sub-ports using time division multiplexing. Each sub-port is allocated a corresponding data transfer capacity.

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract: A verification process comprises a verification environment having a hardware development language interface. The verification process also comprises a device under test having a hardware development language interface operable to communicate with the verification environment hardware development language interface, and also having an Infiniband interface. The verification process additionally comprises a remote Infiniband link having an Infiniband interface operable to communicate with the device under test Infiniband interface and also having a socket protocol interface operable to communicate with a further verification process.