Patents by Inventor Morten Stribaek
Morten Stribaek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8190665Abstract: A microprocessor including random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and probe attacks. A random sequence generator is used to randomize the order in which memory locations are read when filling a cache line.Type: GrantFiled: November 21, 2007Date of Patent: May 29, 2012Assignee: MIPS Technologies, Inc.Inventors: Morten Stribaek, Jakob Schou Jensen, Jean-Francois Dhem
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Patent number: 7911952Abstract: An interface between electronic devices uses a credit-based flow protocol with sustained bus signals. An initiating device waits for credit to issue a command to a target device. When credit is available, the initiating device issues the command to the target device such that the command is accessible by the target device until a new command is issued. The command may include a read or write request to the target device.Type: GrantFiled: July 12, 2002Date of Patent: March 22, 2011Assignee: MIPS Technologies, Inc.Inventors: Flemming Nygreen, Morten Stribaek, Ole Kristian Friis, Kim Mostrup
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Patent number: 7860911Abstract: A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).Type: GrantFiled: April 25, 2006Date of Patent: December 28, 2010Assignee: MIPS Technologies, Inc.Inventors: Morten Stribaek, Pascal Paillier
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Patent number: 7711763Abstract: Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided.Type: GrantFiled: February 21, 2001Date of Patent: May 4, 2010Assignee: MIPS Technologies, Inc.Inventors: Morten Stribaek, Kevin D. Kissell, Pascal Paillier
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Patent number: 7599981Abstract: A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations. To this end, the multiply unit may include an input data path that receives input operands, an arithmetic multiplier connected to receive the input operands, a binary polynomial multiplier having components separate and distinct from the arithmetic multiplier and connected to receive the one or more input operands, and a multiply unit output data path connected to receive an output of the arithmetic multiplier and connected to receive an output of the binary polynomial multiplier. The multiply unit also may include permutation logic that performs permutation operations on the input operands.Type: GrantFiled: February 21, 2001Date of Patent: October 6, 2009Assignee: MIPS Technologies, Inc.Inventors: Hartvig W. J. Ekner, Morten Stribaek, Soeren R. F. Laursen
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Patent number: 7509480Abstract: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers.Type: GrantFiled: December 11, 2006Date of Patent: March 24, 2009Assignee: Mips Technology, Inc.Inventors: Michael Gottlieb Jensen, Morten Stribaek
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Publication number: 20080133629Abstract: A microprocessor including random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and probe attacks. A random sequence generator is used to randomize the order in which memory locations are read when filling a cache line.Type: ApplicationFiled: November 21, 2007Publication date: June 5, 2008Applicant: MIPS Technologies, Inc.Inventors: Morten STRIBAEK, Jakob Schou Jensen, Jean-Francois Dhem
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Patent number: 7318145Abstract: A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be configurable so that the average frequency of random slips generated by the system may be set. Additional techniques are provided to make nullified instructions consume power like any other executing instruction.Type: GrantFiled: May 9, 2002Date of Patent: January 8, 2008Assignee: MIPS Technologies, Inc.Inventors: Morten Stribaek, Jakob Schou Jensen, Jean-Francois Dhem
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Patent number: 7310706Abstract: A microprocessor includes random cache line refill ordering to lessen side channel leakage in a cache line and thus thwart cryptanalysis attacks such as timing attacks, power analysis attacks, and probe attacks. A random sequence generator is used to randomize the order in which memory locations are read when filling a cache line.Type: GrantFiled: May 10, 2002Date of Patent: December 18, 2007Assignee: MIPS Technologies, Inc.Inventors: Morten Stribaek, Jakob Schou Jensen, Jean-Francois Dhem
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Publication number: 20070186130Abstract: The present invention relates to a reduced size format for transmission packet header wherein a source address is encoded together with a check code in a medical device. The packet header thus contains one single field now in place of two i.e. the check code and source address. At the receiving end, the receiver looks up the sender address from the session descriptor table, calculates the check code and then performs the same encoding with the address and the check code, thus authenticating and validating the packet.Type: ApplicationFiled: September 18, 2006Publication date: August 9, 2007Applicant: Novo Nordisk A/SInventors: Per Holm, Per Hansen, Morten Stribaek
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Patent number: 7237097Abstract: Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier.Type: GrantFiled: February 21, 2001Date of Patent: June 26, 2007Assignee: MIPS Technologies, Inc.Inventors: Kevin D. Kissell, Hartvig W. J. Ekner, Morten Stribaek, Jakob Schou Jensen
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Patent number: 7225212Abstract: A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).Type: GrantFiled: July 16, 2002Date of Patent: May 29, 2007Assignee: MIPS Technologies, Inc.Inventors: Morten Stribaek, Pascal Paillier
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Publication number: 20070094482Abstract: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers.Type: ApplicationFiled: December 11, 2006Publication date: April 26, 2007Applicant: MIPS Technologies, Inc.Inventors: Michael Jensen, Morten Stribaek
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Patent number: 7181484Abstract: A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).Type: GrantFiled: February 21, 2001Date of Patent: February 20, 2007Assignee: MIPS Technologies, Inc.Inventors: Morten Stribaek, Pascal Paillier
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Patent number: 7149878Abstract: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers.Type: GrantFiled: October 30, 2000Date of Patent: December 12, 2006Assignee: MIPS Technologies, Inc.Inventors: Michael Gottlieb Jensen, Morten Stribaek
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Publication number: 20060190519Abstract: A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).Type: ApplicationFiled: April 25, 2006Publication date: August 24, 2006Applicant: MIPS Technologies, Inc.Inventors: Morten Stribaek, Pascal Paillier
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Publication number: 20060190518Abstract: A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations.Type: ApplicationFiled: February 21, 2001Publication date: August 24, 2006Inventors: Hartvig Ekner, Morten Stribaek, Soeren Laursen
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Publication number: 20020178203Abstract: A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-purpose register (“MFLHXU”) and an instruction to move the contents of a general-purpose register to a portion of the extended accumulator (“MTLHX”).Type: ApplicationFiled: July 16, 2002Publication date: November 28, 2002Applicant: MIPS Technologies, Inc., a Delaware CorporationInventors: Morten Stribaek, Pascal Paillier
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Publication number: 20020116428Abstract: Polynomial arithmetic instructions are provided in an instruction set architecture (ISA). A multiply-add-polynomial (MADDP) instruction and a multiply-polynomial (MULTP) instruction are provided.Type: ApplicationFiled: February 21, 2001Publication date: August 22, 2002Inventors: Morten Stribaek, Kevin D. Kissell, Pascal Paillier
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Publication number: 20020116602Abstract: Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and a control specifier.Type: ApplicationFiled: February 21, 2001Publication date: August 22, 2002Inventors: Kevin D. Kissell, Hartvig W.J. Ekner, Morten Stribaek, Jakob Schou Jensen