Abstract: A high efficiency search table is implemented with a multiple hash algorithm. The search table allows for exact match searching of arbitrary data sets with fixed latency. The probability of collisions from the hash algorithms is reduced through the use of oversized pointer tables allowing for a level of indirection between hash values and table entries. In the event of a collision in all hash functions, a firmware assisted cuckoo algorithm is employed to resolve the collision.

Abstract: In a Ternary Content Addressable Memory (TCAM) optimized for network packet classification, network operation rules are preprocessed into sub-lists in accordance with a decision tree based packet classification algorithm. The decision tree is encoded as a lookup memory, which is accessed with a predetermined base address of higher order address bits combined with lower order address bits obtained from specific bit positions from a received network packet. Depending on the nodes traversed in the decision tree, different base addresses and values from different bit positions of the packet are used until a sub-list of potential rules is identified. A bitwise comparison of values of each rule against the packet is then executed, the matching rule with the highest precedence is returned as the matching table entry and the configured value associated with the entry is prepended to the packet.

Abstract: A system and method for providing efficient block transfer operations through a test access port uses a Fastdata register. The Fastdata register, in part, emulates a pending process access bit (“PrAcc”) typically found in a Control register associated with the test access port. When a Fastdata access (either a Fastdata upload or a Fastdata download) is requested by a probe coupled to the test access port, the Fastdata register is serially coupled to a data register also associated with the test access port. With these registers so coupled and through the operation of the Fastdata register, downloading and uploading data can be accomplished using a single register operation.

Abstract: A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.