Abstract: An electronic device may be provided with wireless circuitry that includes a phased antenna array. The array may include antennas coupled to power amplifiers. Voltage gain detectors may be coupled around final stages of the amplifiers. The array may transmit a signal within a beam. During transmission, the voltage gain detectors may measure voltage gains of the final stages. Biasing circuitry may adjust bias voltages supplied to the final stages based on the measured voltage gains. The bias adjustments may mitigate the effect of near-field coupling between adjacent antennas and external objects loading the impedance of the set of antennas by different amounts across the phased antenna array by, for example, reducing variation in the voltage gain across the phased antenna array. This may serve to improve performance of the phased antenna array in real time as loading conditions for the array and/or the pointing angle of the beam change.

Abstract: An electronic device may include wireless circuitry with a polar power amplifier. Gate terminals of transistors in a PMOS portion of the amplifier may receive a first local oscillator (LO) signal. Gate terminals of transistors in an NMOS portion of the amplifier may receive a second LO signal. A tunable clock generator may generate the first and second LO signals based on a binary control signal received from a physical layer (PHY) controller. The PHY controller may supply the binary control signal to weighting/enable transistors in inverter banks of the tunable clock generator to dynamically adjust a duty cycle ratio between the first and second LO signals over time. The PHY controller may perform this adjustment based the characteristics of the radio-frequency signal in a manner that optimizes linearity and power consumption by the amplifier over time, even as the characteristics change.

Abstract: Wireless circuitry can have an antenna coupled to a receiving amplifier. The receiving amplifier may be coupled to a local feedback loop configured to reduce the gain of the receiving amplifier for suppressing the signal power when receiving a large input signal. The local feedback loop can include a detector and a feedback controller. The detector may have an input coupled to the receiving amplifier and can output a detected signal. The feedback controller may receive the detected signal and output a corresponding control signal. The control signal can be used to reduce the gain of the receiving amplifier by adjusting one or more components within or coupled to the receiving amplifier. Suppressing large input signals in this way presents no additional parasitic loading to the downlink path and can thus provide overvoltage protection without degrading receiver performance.

Abstract: Wireless circuitry may be provided with amplifier circuitry that includes a set of amplifiers on first and second signal lines and matching circuitry that couples the set of amplifiers to an output. The matching circuitry may include a transformer having a primary winding that extends between the signal lines and a secondary winding that extends between the output and a first terminal. The matching circuitry may include first and second capacitors coupled between the signal lines. The amplifier circuitry may be operable in a full power mode and a reduced power mode. The matching circuitry may include a first switch coupled between the first and second capacitors, a second switch that couples the first terminal to ground, and a third switch that couples a second terminal on the secondary winding to ground. The first, second, and third switches may be adjusted between the full and reduced power modes.

Abstract: An electronic device may be provided with an antenna fed using a Doherty amplifier. The Doherty amplifier may include a main amplifier path with a main amplifier and an auxiliary amplifier path with an auxiliary amplifier. An adaptive biasing circuit may be coupled to the main amplifier path around the main amplifier. The adaptive biasing circuit may include a first voltage detector coupled to an input of the main amplifier, a second voltage detector coupled to an output of the main amplifier, and a subtractor. The first voltage detector may measure an input voltage of the main amplifier. The second voltage detector may measure an output voltage of the main amplifier. The subtractor may generate a difference voltage between the input and output voltages. The auxiliary amplifier may be biased using the difference voltage.

Abstract: Wireless circuitry can have an antenna coupled to a receiving amplifier. The receiving amplifier may be coupled to a local feedback loop configured to reduce the gain of the receiving amplifier for suppressing the signal power when receiving a large input signal. The local feedback loop can include a detector and a feedback controller. The detector may have an input coupled to the receiving amplifier and can output a detected signal. The feedback controller may receive the detected signal and output a corresponding control signal. The control signal can be used to reduce the gain of the receiving amplifier by adjusting one or more components within or coupled to the receiving amplifier. Suppressing large input signals in this way presents no additional parasitic loading to the downlink path and can thus provide overvoltage protection without degrading receiver performance.

Abstract: Wireless circuitry is provided that includes an antenna and a radio-frequency amplifier coupled to the antenna. The radio-frequency amplifier can include a first input transistor having a drain terminal coupled to a first node, a second input transistor having a drain terminal coupled to a second node, and a common mode impedance tuning circuit coupled between the first and second nodes. The common mode impedance tuning circuit can be configured to tune a common mode impedance at the first and second nodes of the radio-frequency amplifier. The common mode impedance tuning circuit can be configured to provide a first common mode impedance when the amplifier is operating in accordance with a first set of operating conditions and can be configured to provide a second common mode impedance, different than the first common mode impedance, when the amplifier is operating in accordance with a second set of operating conditions.

Abstract: Wireless circuitry is provided that includes an antenna and a radio-frequency amplifier coupled to the antenna. The radio-frequency amplifier can include a first input transistor having a drain terminal coupled to a first node, a second input transistor having a drain terminal coupled to a second node, and a common mode impedance tuning circuit coupled between the first and second nodes. The common mode impedance tuning circuit can be configured to tune a common mode impedance at the first and second nodes of the radio-frequency amplifier. The common mode impedance tuning circuit can be configured to provide a first common mode impedance when the amplifier is operating in accordance with a first set of operating conditions and can be configured to provide a second common mode impedance, different than the first common mode impedance, when the amplifier is operating in accordance with a second set of operating conditions.

Abstract: This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.

Abstract: Radio frequency (RF) transmitters of a device (aggressor device) may unintentionally transmit a high-power output signal to antennas of a receiving device (victim device). In some RF systems, a victim device may have no or little protection between its antennas and transistors in an integrated circuit. Performance or lifetime of the transistors may be negatively impacted due to large voltage swings that may result from the high-power signal received from the aggressor device. To prevent or mitigate impact to performance or lifetime of the transistors due to the large voltage swings, protection circuitry including switches and a direct current (DC) power source (e.g., a charge pump) may be implemented at an input of a receiver of the victim device to shunt the power from sensitive circuit components of the victim device.

Abstract: This disclosure is directed to amplifiers including amplification circuitry, phase-shifting circuitry, and impedance matching circuitry. An amplifier may include multiple amplifier stages each amplifying an input signal by a portion of a total amplification factor of the amplifier. The amplifier may include multiple phase shifters each including a matching circuit embedded thereon. Each phase shifter may shift a phase of the input signal by a portion of a total phase shift value of the amplifier. Moreover, at least some phase shifters may provide an output signal at an output port having an output impedance matching (e.g., nearly matching) an input impedance of a subsequent circuit coupled thereto. The amplifier may include cascaded amplifier stages and phase shifters coupled to the subsequent circuit such as an antenna, a processor, and/or a memory device.

Abstract: Radio frequency (RF) transmitters of a device (aggressor device) may unintentionally transmit a high-power output signal to antennas of a receiving device (victim device). In some RF systems, a victim device may have no or little protection between its antennas and transistors in an integrated circuit. Performance or lifetime of the transistors may be negatively impacted due to large voltage swings that may result from the high-power signal received from the aggressor device. To prevent or mitigate impact to performance or lifetime of the transistors due to the large voltage swings, protection circuitry including switches and a direct current (DC) power source (e.g., a charge pump) may be implemented at an input of a receiver of the victim device to shunt the power from sensitive circuit components of the victim device.

Abstract: Wireless circuitry can have an antenna coupled to a receiving amplifier. The receiving amplifier may be coupled to a local feedback loop configured to reduce the gain of the receiving amplifier for suppressing the signal power when receiving a large input signal. The local feedback loop can include a detector and a feedback controller. The detector may have an input coupled to the receiving amplifier and can output a detected signal. The feedback controller may receive the detected signal and output a corresponding control signal. The control signal can be used to reduce the gain of the receiving amplifier by adjusting one or more components within or coupled to the receiving amplifier. Suppressing large input signals in this way presents no additional parasitic loading to the downlink path and can thus provide overvoltage protection without degrading receiver performance.

Abstract: Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/? and I/Q) component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.

Abstract: This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.

Abstract: This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.

Abstract: Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/? and I/Q) component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.

Abstract: Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/? and I/Q component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.

Abstract: A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.

Abstract: A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.