Abstract: In a local area network, a plurality of nodes are connected to a single port of a hub through a length of cable and a corresponding plurality of transceivers attached to the cable, each of the transceivers having an output impedance significantly greater than the cable characteristic impedance, thereby allowing a plurality of nodes to be connected to one hub port with a single cable.

Abstract: A video dot intensity balancer for use in a video display system wherein information is represented by a series of logic bits in a video stream corresponding to dots to be displayed on a CRT is disclosed. Logic elements are coupled to the output of a bit generator for comparing adjacent bits and outputting an information-defining signal wherein a single information-defining bit never stands alone. In this manner, apparent intensity imbalances on the video screen are eliminated.

Abstract: For a microcomputer system including a program memory and a microprocessor having means for executing sets of microinstructions which includes an instruction decoder and a microinstruction memory for storing the sets of microinstructions wherein each set of microinstructions is associated with a publicly known OP code, and wherein each set being activated in response to a related control word there is disclosed a method for securing from unauthorized copying a program stored in the program memory consisting of instruction words, with each instruction word including a control word wherein each of the instruction words is stored in a program memory external to the microprocessor.

Abstract: A microprocessor based CRT video display system includes a microprocessor, a memory and a video processor and controller. The video processor and controller incorporates data and address bus structure in which a plurality of programmable registers are connected to both the data bus and the address bus. The programmable registers arranged along the data and address buses permit efficient retrieval of information from memory for display and also permit the video display system to provide a number of advantageous system features.

Abstract: A display system which has a source of blocks of codes representing characters to be displayed and a display device which converts the blocks of codes to lines of visually displayed characters is provided with a buffer memory which connects the source to the display device. The buffer memory includes a random access memory (RAM) with addressed registers for storing the codes and an address generator in the form of a counter. When a block of codes is transferred from the source to the buffer memory, the counter is initialized and as each code is transmitted to the buffer memory the counter is incremented. Each time the block of codes is transferred from the buffer memory to the display device the counter is again initialized and with the reading of each code from the memory the counter is again incremented. The buffer memory includes two identical RAMs and is controlled such that while one RAM is being loaded the other RAM is being read.

Abstract: In a keyboard having two depressable key switches which receive pulses of a first given width and transmit in response thereto pulses whose width is a function of the mechanical travel of the key switch, the travel of the key switches is detected by feeding a pulse of a first given width alternately to the key switches, sensing for the width of pulses transmitted by the key switches in response to receipt of the pulses of first given width. When the width of a pulse transmitted by one of the key switches in response to the receipt of one of the pulses of the first given width exceeds a second given width which is less than the first given width, there is fed a series of the pulses of first given width only to such one key switch and none of the pulses to the other of the key switches.