Patents by Inventor Mosaddiq Saifuddin
Mosaddiq Saifuddin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240062800Abstract: An effect known as “rowhammer” may be mitigated in a DRAM organized in sub-banks of two or more rows. Row activation commands directed to a sub-bank may be detected. The number of row activation commands occurring within a refresh window may be counted and compared with a threshold. When it is detected that the number of row activation commands within the refresh window exceeds the threshold, an additional refresh command may be provided to the DRAM.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Inventors: Victor Van Der Veen, Pankaj Deshmukh, Behnam Dashtipour, David Hartley, Mosaddiq Saifuddin
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Publication number: 20220129200Abstract: A DRAM memory controller is provided that identifies a marker command directed to a given row in a DRAM. If a threshold probability is satisfied in response to an identification of the marker command, the DRAM memory controller commands the DRAM to refresh a neighboring row in the DRAM. The neighboring row may be a neighboring of the given row or of a recently-closed row.Type: ApplicationFiled: August 17, 2021Publication date: April 28, 2022Inventors: Victor VAN DER VEEN, Mosaddiq SAIFUDDIN, Pankaj DESHMUKH, Behnam DASHTIPOUR, David HARTLEY
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Patent number: 9824742Abstract: Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.Type: GrantFiled: August 26, 2016Date of Patent: November 21, 2017Assignee: QUALCOMM IncorporatedInventors: Mosaddiq Saifuddin, SankaraRao Kunapareddy
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Patent number: 9812222Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.Type: GrantFiled: April 20, 2015Date of Patent: November 7, 2017Assignee: QUALCOMM IncorporatedInventors: Jung Pill Kim, Dexter Tamio Chun, Jungwon Suh, Deepti Vijayalakshmi Sriramagiri, Yanru Li, Mosaddiq Saifuddin, Xiangyu Dong
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Publication number: 20170316818Abstract: Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.Type: ApplicationFiled: August 26, 2016Publication date: November 2, 2017Inventors: Mosaddiq Saifuddin, SankaraRao Kunapareddy
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Patent number: 9754655Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.Type: GrantFiled: November 1, 2016Date of Patent: September 5, 2017Assignee: QUALCOMM IncorporatedInventors: Mosaddiq Saifuddin, SankaraRao Kunapareddy, Keunsoo Roh, Chun Xiang He, Pratik Patel, Nicholas Ambur, Jeremy Haugen
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Publication number: 20170148504Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.Type: ApplicationFiled: November 1, 2016Publication date: May 25, 2017Inventors: Mosaddiq SAIFUDDIN, SankaraRao KUNAPAREDDY, Keunsoo ROH, Chun Xiang HE, Pratik PATEL, Nicholas AMBUR, Jeremy HAUGEN
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Patent number: 9495261Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.Type: GrantFiled: August 12, 2014Date of Patent: November 15, 2016Assignee: QUALCOMM IncorporatedInventors: Jung Pill Kim, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri, Mosaddiq Saifuddin, Xiangyu Dong, Sungryul Kim, Yanru Li, Jungwon Suh
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Publication number: 20160307645Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.Type: ApplicationFiled: April 20, 2015Publication date: October 20, 2016Inventors: Jung Pill KIM, Dexter Tamio CHUN, Jungwon SUH, Deepti Vijayalakshmi SRIRAMAGIRI, Yanru LI, Mosaddiq SAIFUDDIN, Xiangyu DONG
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Patent number: 9379014Abstract: A static random-access memory (SRAM) array includes a first metal layer and a second metal layer. The metal layer includes multiple first source lines spanning multiple columns of cells. The multiple first source lines include a first source line and a second source line. The second metal layer includes multiple second source lines spanning multiple rows of cells. The SRAM array further includes a set of vias coupled to the multiple first source lines and to the multiple second source lines. A first via of the set of vias is coupled to the first source line and multiple vias of the set of vias are coupled to the second source line. Two vias of the multiple vias that are closest to the first via are each substantially the same distance from the first via.Type: GrantFiled: July 18, 2015Date of Patent: June 28, 2016Assignee: QUALCOMM IncorporatedInventors: Niladri Narayan Mojumder, Stanley Seungchul Song, Choh Fei Yeap, Mosaddiq Saifuddin
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Patent number: 9378081Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.Type: GrantFiled: January 2, 2014Date of Patent: June 28, 2016Assignee: Qualcomm IncorporatedInventors: Xiangyu Dong, Jung Pill Kim, Mosaddiq Saifuddin
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Patent number: 9349431Abstract: A method of performing refresh operations on a storage device includes identifying word lines coupled to weak storage elements. The method also includes grouping a plurality of word lines having distinct bank offsets onto a single refresh address. Each of the plurality of word lines is coupled to a corresponding weak storage element. The method further includes performing a refresh of the single refresh address.Type: GrantFiled: March 17, 2015Date of Patent: May 24, 2016Assignee: Qualcomm IncorporatedInventors: Mosaddiq Saifuddin, Jung Pill Kim
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Publication number: 20150261632Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.Type: ApplicationFiled: August 12, 2014Publication date: September 17, 2015Inventors: Jung Pill KIM, Dexter Tamio CHUN, Deepti Vijayalakshmi SRIRAMAGIRI, Mosaddiq SAIFUDDIN, Xiangyu DONG, Sungryul KIM, Yanru LI, Jungwon SUH
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Publication number: 20150186198Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.Type: ApplicationFiled: January 2, 2014Publication date: July 2, 2015Applicant: QUALCOMM IncorporatedInventors: Xiangyu Dong, Jung Pill Kim, Mosaddiq Saifuddin
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Patent number: 8098083Abstract: A multiple-finger off-chip driver (OCD) uses delay between branches of the output stage. The delay between branches is controlled using bias circuitry which compensates for process, temperature, and voltage (PVT) variations, resulting in less variation of slew rate at the output of the OCD. The OCD includes a time domain delay stage; a pre-driver stage; a final driver stage; and a bias circuit, for providing bias voltages to the time domain stage that compensate for process, temperature and voltage (PVT) variations on the time domain stage.Type: GrantFiled: April 2, 2009Date of Patent: January 17, 2012Assignee: Nanya Technology Corp.Inventors: Phat Truong, Mosaddiq Saifuddin, Chia-Jen Chang
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Publication number: 20100253391Abstract: A multiple-finger off-chip driver (OCD) uses delay between branches of the output stage. The delay between branches is controlled using bias circuitry which compensates for process, temperature, and voltage (PVT) variations, resulting in less variation of slew rate at the output of the OCD. The OCD includes a time domain delay stage; a pre-driver stage; a final driver stage; and a bias circuit, for providing bias voltages to the time domain stage that compensate for process, temperature and voltage (PVT) variations on the time domain stage.Type: ApplicationFiled: April 2, 2009Publication date: October 7, 2010Inventors: Phat Truong, Mosaddiq Saifuddin, Chia-Jen Chang