Abstract: Embodiments of the invention relate to a method of indirect printing with an aqueous ink. Related apparatus, systems and treatment formulations are disclosed herein. Some embodiments relate to an aqueous treatment formulation for use with an intermediate transfer member of a printing system. In some embodiments, the system comprises a treatment station disposed downstream of the impression station and upstream of the image forming station for forming a uniform thin layer of a liquid treatment formulation onto a surface of an intermediate transfer member (ITM) at a lower run thereof.

Abstract: A randomization element includes a logic input for inputting a logic signal, a logic output for outputting the input logic signal at a delay and a randomization element. The randomization elements introduces the delay between said logic input and said logic output and operates selectably in static mode and in dynamic mode in accordance with a mode control signal. A logic circuit may be formed with randomization elements interspersed amongst the logic gates, to obtain protection against side channel attacks by inputting a selected control sequence into the randomization elements.

Abstract: A bit generator includes a sampler and a voltage controlled oscillator (VCO) powered by a supply voltage. The sampler outputs a non-deterministic bit series which is generated by sampling an output of the VCO. The randomness of the non-deterministic bit series depends on inherent background noise and/or inherent clock jitter. Optionally, the bit generator does not include noise source circuitry.

Abstract: A randomization element includes a logic input for inputting a logic signal, a logic output for outputting the input logic signal at a delay and a randomization element. The randomization elements introduces the delay between said logic input and said logic output and operates selectably in static mode and in dynamic mode in accordance with a mode control signal. A logic circuit may be formed with randomization elements interspersed amongst the logic gates, to obtain protection against side channel attacks by inputting a selected control sequence into the randomization elements.

Abstract: An RMTL gate includes at least two logic blocks, where at least one of the logic blocks operates in multiple modes. The respective logic block mode(s) are selected by a topology selector which applies mode control signals to the logic blocks in order to obtain a selected topology for logic circuit operation. RMTL logic gates may be cascaded and/or interconnected to form an RMTL logic circuit with multiple logic gates which may operate with dynamically varying topologies. Use of random, semi-random or specified control sequences may protect the logic circuit against security attacks.

Abstract: An RMTL gate includes at least two logic blocks, where at least one of the logic blocks operates in multiple modes. The respective logic block mode(s) are selected by a topology selector which applies mode control signals to the logic blocks in order to obtain a selected topology for logic circuit operation. RMTL logic gates may be cascaded and/or interconnected to form an RMTL logic circuit with multiple logic gates which may operate with dynamically varying topologies. Use of random, semi-random or specified control sequences may protect the logic circuit against security attacks.