Patents by Inventor Moshe Bach

Moshe Bach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
    Patent number: 9052947
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Welc
  • Unified Optimistic and Pessimistic Concurrency Control for a Software Transactional Memory (STM) System
    Publication number: 20140156953
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Application
    Filed: September 16, 2013
    Publication date: June 5, 2014
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Welc
  • Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
    Patent number: 8555016
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Wele
  • UNIFIED OPTIMISTIC AND PESSIMISTIC CONCURRENCY CONTROL FOR A SOFTWARE TRANSACTIONAL MEMORY (STM) SYSTEM
    Publication number: 20100153953
    Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Inventors: Ali-Reza Adl-Tabatabai, Moshe Bach, Sion Berkowits, James Henry Cownie, Yang Ni, Jeffrey V. Olivier, Bratin Saha, Ady Tal, Adam Wele
  • Load balancing of network by maintaining in each computer information regarding current load on the computer and load on some other computers in the network
    Patent number: 5539883
    Abstract: A method is described of operating a computer in a network of computers using an improved load balancing technique. Logical links are generated between the computer and other computers in the network so that a tree structure is formed, the computer being logically linked to one computer higher up the tree and a number of computers lower down the tree. Stored information is maintained in the computer regarding the current load on the computer and the load on at least some of the other computers in the network by causing the computer periodically to distribute the information to the computers to which it is logically linked, and to receive from the computers similar such information and to update its own information in accordance therewith, so that the information can be used to determine a computer in the network that can accept extra load.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: David Allon, Moshe Bach, Yosef Moatti, Abraham Teperman