Abstract: A method and system for providing Layer 1 time division multiplexing (TDM) framing, multiplexing, and mapping as well as Layer 2 data and protocol processing. One embodiment of the invention provides an integrated Layer1/Layer2 service aggregator within a single-device. Such an embodiment provides a complete System-on-Chip implementation for clear channel and deeply channelized OC-48 (STM-16), 4×OC12/3 (STM4/1) application of 2,000 channels or more. One embodiment implements functionality of Layer2 data and protocol processing as well as Layer1 TDM framing, multiplexing and mapping. For one embodiment, target applications include packet-based transport systems, multi-service access and metro systems, switches and routers and ADM/MSPP systems.

Abstract: A method and system for providing multi-channel circuit emulation clock recovery wherein a single instance of the clock recovery logic effects circuit emulation clock recovery for multiple channels. For one embodiment of the invention, fine tuning clocking is effected by comparing an outgoing clock with a recovered clock and switching a clock recovery mechanism, the switching performed in conjunction with a multi-channel context.

Abstract: A system and method for processing an extremely high data rate datastream. Embodiments of the invention provide methods for performing various operations on the datastream in order to map the datastream from one protocol to another as well as providing methods for processing multiple channels of a given protocol. For one embodiment of the invention a portion of a datastream is received to a stream buffer. A data stream window is then created from the received portion, the data stream window containing data of more than one protocol. A corresponding portion of the data of a same protocol, is accessed through each of a plurality of processing machines. The accessed data is concurrently processed at each of the processing machines.

Abstract: A method and system for providing Layer 1 time division multiplexing (TDM) framing, multiplexing, and mapping as well as Layer 2 data and protocol processing. One embodiment of the invention provides an integrated Layer1/Layer2 service aggregator within a single-device. Such an embodiment provides a complete System-on-Chip implementation for clear channel and deeply channelized OC-48 (STM-16), 4×OC12/3 (STM4/1) application of 2,000 channels or more. One embodiment implements functionality of Layer2 data and protocol processing as well as Layer1 TDM framing, multiplexing and mapping. For one embodiment, target applications include packet-based transport systems, multi-service access and metro systems, switches and routers and ADM/MSPP systems.

Abstract: A method and system for providing multi-channel circuit emulation clock recovery wherein a single instance of the clock recovery logic effects circuit emulation clock recovery for multiple channels. For one embodiment of the invention, fine tuning clocking is effected by comparing an outgoing clock with a recovered clock and switching a clock recovery mechanism, the switching performed in conjunction with a multi-channel context.

Abstract: A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.

Abstract: System and method for dynamically altering bandwidth allocation to each region serviced by a network. Each region is allocated an initial estimated bandwidth on the network and compares instantaneous demand against the allocation. When demand falls below the allocation, the region releases bandwidth so other regions can take advantage of that bandwidth. When demand exceeds the allocation, the region takes advantage of bandwidth released by other regions.

Abstract: A system and method for processing an extremely high data rate datastream. Embodiments of the invention provide methods for performing various operations on the datastream in order to map the datastream from one protocol to another as well as providing methods for processing multiple channels of a given protocol. For one embodiment of the invention a portion of a datastream is received to a stream buffer. A data stream window is then created from the received portion, the data stream window containing data of more than one protocol. A corresponding portion of the data of a same protocol, is accessed through each of a plurality of processing machines. The accessed data is concurrently processed at each of the processing machines.

Abstract: A link layer controller comprises a network layer interface, a physical layer interface, and a memory controller. The network layer interface exchanges packets with the network layer system and transfers a status signal to the network layer system. The physical layer interface exchanges the packets with the physical layer system. The memory controller exchanges the packets with the network layer interface, a memory, and the physical layer interface. The memory controller also generates the status signal to indicate available space in the memory.

Abstract: Alternate routing tables selected according to data packet priority or according to source and destination addresses of data packet. Data packet propagated to egress port according to indicator provided by selected routing table with expediency dictated by data packet priority or priority indicator stored in the selected routing table.

Abstract: A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.

Abstract: System and method for dynamically altering bandwidth allocation to each region serviced by a network. Each region is allocated an initial estimated bandwidth on the network and compares instantaneous demand against the allocation. When demand falls below the allocation, the region releases bandwidth so other regions can take advantage of that bandwidth. When demand exceeds the allocation, the region takes advantage of bandwidth released by other regions.

Abstract: A system for controlling the transmission of cells from a network node over multiple Virtual Circuits (VCs) is disclosed. The system performs traffic shaping, as required by connection based systems such as Asynchronous Transfer Mode (ATM), for each VC connected with a network node, so that the Quality of Service (Qos) parameters established when the connection was established are not exceeded. The system includes a process for scheduling the transmission of cells from the network node. The scheduling process periodically scans a table having entries corresponding to virtual circuits connected with the network node. During each scan of the table, the scheduler increments a sustainable rate accumulator field and a peak rate accumulator field of each table entry that corresponds with a virtual circuit that is open, and for which there is a cell ready to be transmitted.

Abstract: A system for controlling the transmission of cells from a network node over multiple virtual circuit is disclosed. The disclosed system performs traffic shaping for all virtual circuits connected with the network node. The system includes a virtual circuit table with one or more entries. Each virtual circuit table entry corresponds to a virtual circuit established with the network node. Each virtual circuit table further includes one or more Cell Rate Accumulator fields and a Time Stamp field. The system includes a schedule table having one or more entries. Each schedule table entry further includes one or more Cell Rate Accumulator fields and corresponding predetermined value fields. A schedule table loading process determines a virtual circuit on which a packet is to be transmitted, and then calculates a time elapsed since a last previous write of a virtual circuit table entry corresponding with that virtual circuit.

Abstract: The invention improves the efficiency of buffer descriptor processing by performing descriptor prefetches, where multiple descriptors are read within the same descriptor bus transaction. The invention reads multiple buffer descriptors each time the bus is accessed. This allows for a smaller FIFO in a cut-through network adapter because it reduces the number of bus transactions needed to transfer data.

Abstract: A system for controlling the transmission of cells from a network node over multiple Virtual Circuits (VCs) is disclosed. The system performs traffic shaping, as required by connection based systems such as Asynchronous Transfer Mode (ATM), for each VC connected with a network node, so that the Quality of Service (Qos) parameters established when the connection was established are not exceeded. The system includes a process for scheduling the transmission of cells from the network node. The scheduling process periodically scans a table having entries corresponding to virtual circuits connected with the network node. During each scan of the table, the scheduler increments a sustainable rate accumulator field, a peak rate accumulator field, and a latency accumulator field of each table entry that corresponds with a virtual circuit that is open, and for which there is a cell ready to be transmitted.