Abstract: A system and method for enabling concurrent usage of non-volatile memory for code execution and data storage/processing, comprising a hardware mechanism that can support automatic suspend and resume operations. This mechanism entails the integration of a suspend logic circuit and a resume logic circuit into the chip hardware, or the stationing of the logic chip in any way that it can operate together with the chip. This system and method enable a Flash memory chip to process code execution while it is processing erase/program operations, avoiding conflicts that ordinarily crash such a system. This is achieved by sensing the operation status of the chip and the CPU/Bus activity, and commanding the flash memory device to suspend and/or resume program/erase operations at appropriate times, so as not to conflict with read requests.

Abstract: Systems and methods relating to semiconductor testing and programming, including semiconductor-chip testing apparatuses, semiconductor-chip programming apparatuses, semiconductor testing integrated-circuit chips (“TIC's”), employable in testing and/or programming semiconductor integrated circuits. Such TICS may be full testers, capable of performing tests such as AC, DC, functional, and mixed signal (analog) tests, and/or may be capable of performing design verification and/or characterization.

Abstract: According to the present invention, there is provided a system for enabling code execution from a Non-executable memory. The present invention combines a small amount of an executable memory with a large amount of non-executable memory, in order to enable a highly efficient executable data and code storage system, comprised of relatively cheap non-executable memory components.