Abstract: Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.

Abstract: Some demonstrative embodiments of the invention include a method, apparatus and system of generating a random number. A random number generator may include, for example, a plurality of different random-number-generation modules adapted to generate random bits at a plurality of bit paths; and a combiner adapted to combine the bits of the plurality of paths. Other embodiments are described and claimed.

Abstract: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Abstract: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “?”-type filter arrangement, wherein n=1, 2, 3, . . . , }.

Abstract: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Abstract: The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “?”-type filter arrangement, wherein n=1, 2, 3, . . . , }.

Abstract: A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.

Abstract: The present invention is a method and system for schematically embedding wire model objects into a schematic design of an integrated circuit. The method includes estimating a wiring routing geometry for each signal path in the circuit, selecting one or more cascading wire model objects (“WMOs”) for each segment in each geometry, and substituting each signal path with the respective one or more WMOs.

Abstract: Apparatus for multiplexing electronic data-words provided by a plurality of input sources operating in accordance with respective input clocks which may be mutually asynchronous. The data-words are multiplexed to a common output operating in accordance with a system clock. The apparatus includes delay circuitry, which generates a plurality of select signals responsive to the system clock, corresponding respectively to the plurality of input sources. The apparatus also includes a plurality of synchronizers respectively associated with the plurality of input sources, each synchronizer including a series of memory buffers through which data-words from the respective input source are transferred. The series of memory buffers includes at least an input buffer, which receives the data-words from the respective input source in accordance with the respective input clock, and an output buffer, which provides the data-words for output in accordance with the corresponding select signal.

Abstract: An analog-to-digital converter, including a code generator, coupled to receive an input analog voltage and to one or more reference voltages, and adapted to generate a digital code responsive thereto, and one or more folded differential logic encoders (FDLEs) . Each of the FDLEs includes a plurality of capacitors and switching logic. The switching logic is coupled to receive the digital code and distribute a charge between the plurality of capacitors responsive to the received digital code, and to output a digital bit indicative of the input analog voltage responsive to a magnitude of a potential generated by the distributed charge on at least one of the plurality of capacitors.

Abstract: An integrated circuit device, including a substrate and a signal source disposed on the substrate. The signal. source is adapted to supply a pair of signals to a first plulrality of customers positioned remote from the signal source on the substrate, each of which customers is adapted to receive the pair of signals. There are a second plurality of conductors, formed substantially within a single layer of conductive material deposited on the substrate, and arranged to distribute the pair of signals from the signal source to each of the customers.

Abstract: In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said steps. Generation of each step is performed in two stages, where in a first stage all facilities and parameters required for the execution of the respective step are defined and assigned the proper values, and where in a second stage the execution of the particular step is performed. This process is continued until a test pattern with the number of steps requested by the user is generated, so that finally the test pattern comprises three parts: The initialized facilities define the initial machine state and execution parts of the test pattern, and the values of the facilities which have been changed during the execution of the steps, form the results part of the test pattern.