Abstract: A method includes measuring a topography of a semiconductor wafer. A distortion function is generated based on the measured topography. Measured alignment data associated with the semiconductor wafer is adjusted using the distortion function. At least one correction factor for an exposure tool is generated based on the adjusted alignment data. The exposure tool is configured based on the at least one correction factor.

Abstract: A system, method, and computer program product are provided for systematic and stochastic characterization of pattern defects identified from a fabricated component. In use, a plurality of pattern defects detected from a fabricated component are identified. Additionally, attributes of each of the pattern defects are analyzed, based on predefined criteria. Further, a first set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be systematic pattern defects, and a second set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be stochastic pattern defects. Moreover, a first action is performed for the determined systematic pattern defects and a second action is performed for the determined stochastic pattern defects.

Abstract: A system, method, and computer program product are provided for systematic and stochastic characterization of pattern defects identified from a fabricated component. In use, a plurality of pattern defects detected from a fabricated component are identified. Additionally, attributes of each of the pattern defects are analyzed, based on predefined criteria. Further, a first set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be systematic pattern defects, and a second set of pattern defects of the plurality of pattern defects are determined, from the analysis, to be stochastic pattern defects. Moreover, a first action is performed for the determined systematic pattern defects and a second action is performed for the determined stochastic pattern defects.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

Abstract: An automated method for co-optimizing a scatterometry mark and a process monitoring mark is provided. Embodiments include generating a series of pattern profiles on a photoresist on a wafer; providing the series of pattern profiles, resist process parameters, and scatterometry critical dimension parameters as inputs for a scatterometry measurement; performing scatterometry measurement to generate spectra from the series of pattern profiles; and optimizing a sensitivity precision correlation for the resist process parameter.

Abstract: An overlay method for determining the overlay error of a device structure formed during semiconductor processing is disclosed. The overlay method includes producing calibration data that contains overlay information relating the overlay error of a first target at a first location to the overlay error of a second target at a second location for a given set of process conditions. The overlay method also includes producing production data that contains overlay information associated with a production target formed with the device structure. The overlay method further includes correcting the overlay error of the production target based on the calibration data.

Abstract: Disclosed are apparatus and methods for monitoring a characteristic associated with a product feature on a semiconductor product. A proxy target formed from at least one substructure that corresponds to a product feature is provided. The substructure is not individually resolvable by an optical tool. A characteristic of the proxy target is determined based on optically monitoring the proxy target using the optical tool. Based on the determined characteristic of the proxy target, it is then determined whether the corresponding product feature has a characteristic that is within a predetermined specification or whether a process parameter used to fabricate such product feature is within a predetermined specification. In a specific embodiment, the characteristic of the corresponding product feature includes a shape parameter and a position parameter.

Abstract: A method for identifying process window signature patterns in a device area of a mask is disclosed. The signature patterns collectively provide a unique response to changes in a set of process condition parameters to the lithography process. The signature patterns enable monitoring of associated process condition parameters for signs of process drift, analyzing of the process condition parameters to determine which are limiting and affecting the chip yields, analyzing the changes in the process condition parameters to determine the corrections that should be fed back into the lithography process or forwarded to an etch process, identifying specific masks that do not transfer the intended pattern to wafers as intended, and identifying groups of masks that share common characteristics and behave in a similar manner with respect to changes in process condition parameters when transferring the pattern to the wafer.

Abstract: Computer-implemented methods and systems for detecting defects in a reticle design pattern are provided. One computer-implemented method includes acquiring images of a field in the reticle design pattern. The images illustrate how the field will be printed on a wafer at different values of one or more parameters of a wafer printing process. The field includes a first die and a second die. The method also includes detecting defects in the field based on a comparison of two or more of the images corresponding to two or more of the different values. In addition, the method includes determining if individual defects located in the first die have substantially the same within die position as individual defects located in the second die.

Abstract: A method of using an in-situ aerial image sensor array is disclosed to separate and remove the focal plane variations caused by the image sensor array non-flatness and/or by the exposure tool by collecting sensor image data at various nominal focal planes and by determining best focus at each sampling location by analysis of the through-focus data. In various embodiments, the method provides accurate image data at best focus anywhere in the exposure field, image data covering an exposure-dose based process window area, and a map of effective focal plane distortions. The focus map can be separated into contributions from the exposure tool and contributions due to topography of the image sensor array by suitable calibration or self-calibration procedures. The basic method enables a wide range of applications, including for example qualification testing, process monitoring, and process control by deriving optimum process corrections from analysis of the image sensor data.

Abstract: One embodiment of a method for detecting, sampling, analyzing, and correcting hot spots in an integrated circuit design allows the identification of the weakest patterns within each design layer, the accurate determination of the impact of process drifts upon the patterning performance of the real mask in a real scanner, and the optimum process correction, process monitoring, and RET improvements to optimize integrated circuit device performance and yield. The combination of high speed simulation coupled with massive data collection capability on actual aerial images and/or resist images at the specific patterns of interest provides a complete methodology for optimum RET implementation and process monitoring.

Abstract: Computer-implemented methods for detecting defects in reticle design data are provided. One method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. The method further includes detecting defects in the reticle design data using the second simulated images. Another method includes the generating steps described above in addition to determining a rate of change in a characteristic of the second simulated images as a function of the different values. This method also includes detecting defects in the reticle design data based on the rate of change.

Abstract: Various computer-implemented methods are provided. One method for evaluating reticle layout data includes generating a simulated image using the reticle layout data as input to a model of a reticle manufacturing process. The simulated image illustrates how features of the reticle layout data will be formed on a reticle by the reticle manufacturing process. The method also includes determining manufacturability of the reticle layout data using the simulated image. The manufacturability is a measure of how accurately the features will be formed on the reticle. Also provided are various carrier media that include program instructions executable on a computer system for performing a method for evaluating reticle layout data as described herein. In addition, systems configured to evaluate reticle layout data are provided. The systems include a computer system and a carrier medium that includes program instructions executable on the computer system for performing method(s) described herein.

Abstract: An overlay method for determining the overlay error of a device structure formed during semiconductor processing is disclosed. The overlay method includes producing calibration data that contains overlay information relating the overlay error of a first target at a first location to the overlay error of a second target at a second location for a given set of process conditions. The overlay method also includes producing production data that contains overlay information associated with a production target formed with the device structure. The overlay method further includes correcting the overlay error of the production target based on the calibration data.