Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

Abstract: Technologies are disclosed for using hardware-embedded monitors to monitor pages of local memory and detect attribute violations or other unauthorized operations relating to the memory. The attribute violations may include mismatches of attributes (e.g., designating a page as writeable versus executable or vice versa) in entries in a translation buffer that point to a same physical address or other mismatches between designations of attributes for a page in physical and virtual space. Responsive to detecting a violation, an alert or other mitigation protocol, which may include an audit of activities surrounding the violation, may be performed.

Abstract: Systems and methods are provided to improve system performance when multiple transaction retry events associated with transaction requests from requester nodes to completer nodes are detected. A retry monitor can monitor the transaction retry events associated with the transaction requests to provide retry information. An intervention level generator can receive information about the transaction retry events and determine an intervention level from a plurality of intervention levels based on the retry information and a retry configuration. Each requester node can be coupled to a regulator to regulate the transactions being requested by that requester node based on the intervention level and a regulator configuration, which can allow the corresponding completer nodes to complete the outstanding transactions and reduce the occurrence of retry events.

Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

Abstract: A write cleaner circuit can be used to implement write-through (WT) functionality by a write-back (WB) cache memory for updating the system memory. The write cleaner circuit can intercept memory write transactions issued to the WB cache memory and generate clean requests that can enable the WB cache memory to send update requests to corresponding memory locations in the system memory around the same time as the memory write transactions are performed by the WB cache memory, and clear dirty bits in the cache lines corresponding to those memory write transactions.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: A processing apparatus includes multiple Central Processing Units (CPUs) and a coherence fabric. Respective ones of the CPUs include respective local cache memories and are configured to perform memory transactions that exchange cache-lines among the local cache memories and a main memory that is shared by the multiple CPUs. The coherence fabric is configured to identify and record in a centralized data structure, per cache-line, an identity of at most a single cache-line-owner CPU among the subset of CPUs that is responsible to commit the cache-line to the main memory; and to serve at least a memory transaction from among the memory transactions, which pertains to a given cache-line among the cache-lines, based on the identity of the cache-line-owner CPU of the cache-line, as recorded in the centralized data structure.

Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: A method and system are disclosed that permit a host application to obtain cluster location data, for example logical addresses associated with the clusters of a file, and to allow a host application to communicate the logical block address mapping information to firmware of a storage device. The method includes the host transmitting one or more clusters or partial clusters having a signature to the storage device where the storage device knows or has been instructed by the host to look for the signature. The storage device may receive clusters having a signature and, responsive to a host request, return logical address information to a host for the location in the storage device of the marked clusters. The host may parse a data structure on the storage device to obtain remaining cluster location information using a file's first cluster location or may request that the storage device return the cluster location information.

Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.

Abstract: Attachments for a manual wheelchair are provided for navigating a wheelchair over obstacles and uneven terrain, such as a typical curb on a street. The attachments provide for regulating the movement of the wheelchair as the wheelchair descends the curb and to prevent the wheelchair from flipping over during such movement. The attachments include a belt support frame, at least two rollers mounted on the belt support frame and a belt mounted around the at least two rollers. The belt support frame is adapted for mounting on the frame of the wheelchair such that as the wheelchair descends from the upper surface to the lower surface, the belt engages an edge of the upper surface and rolls around the at least two rollers slowing a descent of the wheelchair from the upper surface to the lower surface.

Abstract: A method and system are disclosed that permit a host application to obtain cluster location data, for example logical addresses associated with the clusters of a file, and a host application to communicate the logical block address mapping information to firmware of a storage device. The method includes the host transmitting one or more clusters or partial clusters having a signature to the storage device where the storage device knows or has been instructed to look for the signature. The storage device may receive clusters having a signature and, responsive to a host request, return logical address information to a host for the location in the storage device of the marked clusters. The host may parse a data structure on the storage device to obtain remaining cluster location information using a file's first cluster location or may request that the storage device return the cluster location information.

Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.