Patents by Inventor Moshe Raz
Moshe Raz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11936393Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.Type: GrantFiled: June 6, 2022Date of Patent: March 19, 2024Assignee: Amazon Technologies, Inc.Inventors: Guy Nakibly, Moshe Raz, Zvika Glaubach
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Patent number: 11916361Abstract: A threading accessory comprising a belt and two rotatable wheels configured to revolve the belt which has a circumferential groove formed in an outer face thereof and configured to receive and hold a portion of a thread therein. One or more press-wheels are used to engage a portion of the belt passing between the rotating wheels and elastically deform the belt portion to thereby at least partially wrap it about and latch the thread portion inside in the circumferential groove for propulsion by the belt.Type: GrantFiled: January 25, 2023Date of Patent: February 27, 2024Assignee: S.T.B.M.K. LTDInventors: Yakov Bar, Moshe Agami, Itay Raz
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Patent number: 11860781Abstract: A write cleaner circuit can be used to implement write-through (WT) functionality by a write-back (WB) cache memory for updating the system memory. The write cleaner circuit can intercept memory write transactions issued to the WB cache memory and generate clean requests that can enable the WB cache memory to send update requests to corresponding memory locations in the system memory around the same time as the memory write transactions are performed by the WB cache memory, and clear dirty bits in the cache lines corresponding to those memory write transactions.Type: GrantFiled: May 4, 2022Date of Patent: January 2, 2024Assignee: Amazon Technologies, Inc.Inventors: Moshe Raz, Guy Nakibly, Gal Avisar
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Patent number: 10230542Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: GrantFiled: March 8, 2017Date of Patent: March 12, 2019Assignee: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
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Publication number: 20180074960Abstract: A processing apparatus includes multiple Central Processing Units (CPUs) and a coherence fabric. Respective ones of the CPUs include respective local cache memories and are configured to perform memory transactions that exchange cache-lines among the local cache memories and a main memory that is shared by the multiple CPUs. The coherence fabric is configured to identify and record in a centralized data structure, per cache-line, an identity of at most a single cache-line-owner CPU among the subset of CPUs that is responsible to commit the cache-line to the main memory; and to serve at least a memory transaction from among the memory transactions, which pertains to a given cache-line among the cache-lines, based on the identity of the cache-line-owner CPU of the cache-line, as recorded in the centralized data structure.Type: ApplicationFiled: September 7, 2017Publication date: March 15, 2018Inventor: Moshe Raz
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Patent number: 9760299Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.Type: GrantFiled: February 23, 2015Date of Patent: September 12, 2017Assignee: SanDisk Technologies LLCInventors: Rotem Sela, Moshe Raz, Paul Yaroshenko
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Publication number: 20170180156Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: March 8, 2017Publication date: June 22, 2017Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
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Patent number: 9521011Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: GrantFiled: January 22, 2014Date of Patent: December 13, 2016Assignee: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Moshe Raz, Amit Shmilovich
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Patent number: 9152641Abstract: A method and system are disclosed that permit a host application to obtain cluster location data, for example logical addresses associated with the clusters of a file, and to allow a host application to communicate the logical block address mapping information to firmware of a storage device. The method includes the host transmitting one or more clusters or partial clusters having a signature to the storage device where the storage device knows or has been instructed by the host to look for the signature. The storage device may receive clusters having a signature and, responsive to a host request, return logical address information to a host for the location in the storage device of the marked clusters. The host may parse a data structure on the storage device to obtain remaining cluster location information using a file's first cluster location or may request that the storage device return the cluster location information.Type: GrantFiled: December 15, 2011Date of Patent: October 6, 2015Assignee: SanDisk Technologies Inc.Inventors: Joseph Edward Halpern, III, Henry Hutton, Judah Gamliel Hahn, Moshe Raz, In-Soo Yoon
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Publication number: 20150199145Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.Type: ApplicationFiled: February 23, 2015Publication date: July 16, 2015Applicant: San Disk Technologies, Inc.Inventors: Rotem Sela, Moshe Raz, Paul Yaroshenko
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Patent number: 9050230Abstract: Attachments for a manual wheelchair are provided for navigating a wheelchair over obstacles and uneven terrain, such as a typical curb on a street. The attachments provide for regulating the movement of the wheelchair as the wheelchair descends the curb and to prevent the wheelchair from flipping over during such movement. The attachments include a belt support frame, at least two rollers mounted on the belt support frame and a belt mounted around the at least two rollers. The belt support frame is adapted for mounting on the frame of the wheelchair such that as the wheelchair descends from the upper surface to the lower surface, the belt engages an edge of the upper surface and rolls around the at least two rollers slowing a descent of the wheelchair from the upper surface to the lower surface.Type: GrantFiled: March 20, 2012Date of Patent: June 9, 2015Assignees: Montefiore Medical Center, The University of HartfordInventors: Avital Fast, Devdas Shetty, Moshe Raz, Giora Rothman
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Patent number: 8984032Abstract: A method and system are disclosed that permit a host application to obtain cluster location data, for example logical addresses associated with the clusters of a file, and a host application to communicate the logical block address mapping information to firmware of a storage device. The method includes the host transmitting one or more clusters or partial clusters having a signature to the storage device where the storage device knows or has been instructed to look for the signature. The storage device may receive clusters having a signature and, responsive to a host request, return logical address information to a host for the location in the storage device of the marked clusters. The host may parse a data structure on the storage device to obtain remaining cluster location information using a file's first cluster location or may request that the storage device return the cluster location information.Type: GrantFiled: December 15, 2011Date of Patent: March 17, 2015Assignee: SanDisk Technologies Inc.Inventors: Joseph Edward Halpern, III, Henry Hutton, Judah Gamliel Hahn, Moshe Raz, In-Soo Yoon
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Patent number: 8966201Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.Type: GrantFiled: December 10, 2010Date of Patent: February 24, 2015Assignee: SanDisk Technologies Inc.Inventors: Rotem Sela, Moshe Raz, Paul Yaroshenko
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Publication number: 20140201472Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Amit Shmilovich, Moshe Raz, Shaul Chapman, Erez Amit
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Publication number: 20140201444Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Moshe Raz, Amit Shmilovich
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Publication number: 20140201443Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Moshe Raz, Husam Khshaiboun
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Publication number: 20140201326Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 15, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
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Patent number: 8683148Abstract: Data storage devices and methods are disclosed that provide a status indication when a maintenance operation is to be performed prior to completion of a write command. A method includes receiving a write command from a host device to write data to the non-volatile memory while the data storage device is operatively coupled to the host device. In response to determining that a maintenance operation is to be performed prior to the completion of the write command, an indication is sent to the host device that the write command has a status of incomplete.Type: GrantFiled: June 30, 2010Date of Patent: March 25, 2014Assignee: Sandisk IL Ltd.Inventors: Moshe Raz, Michael Fong
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Patent number: 8595465Abstract: Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.Type: GrantFiled: September 8, 2010Date of Patent: November 26, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventor: Moshe Raz
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Publication number: 20130159362Abstract: A method and system are disclosed that permit a host application to obtain cluster location data, for example logical addresses associated with the clusters of a file, and a host application to communicate the logical block address mapping information to firmware of a storage device. The method includes the host transmitting one or more clusters or partial clusters having a signature to the storage device where the storage device knows or has been instructed to look for the signature. The storage device may receive clusters having a signature and, responsive to a host request, return logical address information to a host for the location in the storage device of the marked clusters. The host may parse a data structure on the storage device to obtain remaining cluster location information using a file's first cluster location or may request that the storage device return the cluster location information.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Inventors: Joseph Edward Halpern, III, Henry Hutton, Judah Gamliel Hahn, Moshe Raz, In-Soo Yoon