Abstract: A multi-mode mobile communication device capable of communicating with more than one mobile communication system simultaneously has a timer (400) for arbitrating between transmit events of two communication systems. The mobile communication device assigns a priority to each of the two communication systems, and when a transmit event conflict arises, it is resolved in favor of the system having the higher priority. The timer includes a delta timer (426) for timing the duration of transmit events. If the mobile communication device is engaged in a transmit event in one system, and a transmit event arises in the second system, the mobile communication device checks the delta timer. If the timer is not zeroed, the mobile communication device then checks priority of the events, and transmits whichever event has priority.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: The invention provides an apparatus and a method for generating spread spectrum clock signals, the method comprising the steps of: (1.a) determining a relationship R between a fundamental period T of a clock signal and a period offset DT; (1.b) receiving a clock signal having the fundamental period T; (1.c) of adjusting the delay step DS so that the spread spectrum clock signal to be produced during step (1.d) has a period that ranges between (T−DT) and (T+DT). (1.d) producing a spread spectrum clock signal having a period that ranges between (T−DT) and (T+DT). Steps (1.c) and (1.d) can be repeated either constantly, in manner that compensated for either variations in the delay step, in the variable delay period and/or for changes in the fundamental period.

Abstract: A radio (10) with a burst event execution and time synchronization apparatus (16) executes instructions during and after performing time synchronization between a mobile unit and a base station. Both base station (12) and mobile radio (10) have internal timer units (26, 16). Mobile radio (10) timing unit (16) is reset during synchronization between the mobile radio (10) and the base station (12). The control unit (18) writes instructions I(i) including their execution times T(i) to a memory bank (42) within the mobile radio (10). Execution logic (32) within mobile radio (10) executes instruction operands O(i) when execution time T(i) is equal or smaller then a timing count signal received from the timer unit (16). When a time synchronization reset causes the radio (10) time count to jump past queued instructions they can be executed immediately in a burst or delayed until the next communication frame.

Abstract: A multi-mode mobile communication device capable of communicating with more than one mobile communication system simultaneously has a timer (400) for arbitrating between transmit events of two communication systems. The mobile communication device assigns a priority to each of the two communication systems, and when a transmit event conflict arises, it is resolved in favor of the system having the higher priority. The timer includes a delta timer (426) for timing the duration of transmit events. If the mobile communication device is engaged in a transmit event in one system, and a transmit event arises in the second system, the mobile communication device checks the delta timer. If the timer is not zeroed, the mobile communication device then checks priority of the events, and transmits whichever event has priority.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture.

Abstract: A mobile radio (10) with a synchronization apparatus (14) executes a method (60) for time synchronizing the radio (10) and a base station (12). Base station (12) and radio (10) have internal timers (26, 16). A control unit (18) in the radio (10) receives a signal (29) from the base station (12) and determines the difference F between timers (26, 16, 30) in the base (12) and mobile (10). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the radio (10). One of these instructions I(N) reloads the radio timing counter (30) with a corrected value C=f(F,B) at a predetermined time T(N)=B which avoids conflicts with other operations of the radio (10).

Abstract: A radio (10) executes a method (100) for entering and exiting a halt status. Radio (10) has a control unit (18) and an internal timing unit (16). The timing unit (16) has execution logic (32), a status register (46) a counter (30) and a clock source (37). The control unit (18) writes instructions I(i) and their execution times T(i) to a memory (42) within the execution logic (32). One of these instructions is a ‘SWITCH CLOCK’ instruction causing the timing unit (16) to switch between clock signals. One of the instructions is ‘HALT COUNTER’ causing the radio (10) to enter a halt state. The radio (10) can be synchronized to the end of a first communication frame received by it after exiting a halt state.

Abstract: A communications system includes multiple processors (14, 16) and a protocol timer (18). The protocol timer (18) controls the timing of events in the communications system and operates autonomously after it is loaded with initial instructions by one of the multiple processors (14, 16). The protocol timer (18) utilizes a frame event table (50) and a macro event table (46, 48) to trigger events and to generate interrupts of the multiple processors (14, 16). By allowing the protocol timer (18) to operate autonomously, the processors (14, 16) are relieved of timing control, and can be powered down when not in use, thus reducing power consumption of the communications system. Also, by using the protocol timer (18) to control the timing of events, software related errors and interrupt latencies are reduced.