Abstract: A computer-implemented method of compressing data entries in a database, including the steps of: (a) inputting a plurality of uncompressed data entries; (b) dividing a particular uncompressed data entry, in a pre-determined manner, into at least two sections of significant bits, the two sections including both a common section and a differentiating section with respect to other the uncompressed data entries; (c) determining, by comparison of the particular data entry with a monotonically-adjacent entry, if a match exists in the common section; and (d) providing a particular compressed entry for the particular data entry, the compressed entry including compressed data corresponding to the particular data entry, wherein if, in step (c), the match exists in the common section, the compressed data includes at least a portion of the differentiating section of the particular data entry.

Abstract: A computer-implemented method for flexibly storing data in a database so as to allow facile updating and maintenance of the database, including the steps of: (a) providing a first array having rows and columns for storing a first plurality of key entries; (b) arranging the key entries within each of the rows in a monotonic order; (c) providing a second array for storing a second plurality of key entries having rows and at least one column, such that the first and second arrays form a hierarchical structure, wherein the second plurality of entries represents a higher level of the hierarchical structure with respect to the first plurality of entries; (d) identifying an update position for performing a database update operation, and (e) performing the update operation by rearranging a portion of the first plurality of entries.

Abstract: A method for compressing the dynamic range of an image sensor (202) including a multiplicity of pixels. The method includes the steps of exposing each of the pixels to light and producing an associated photocurrent per pixel, representative of the light exposure. Then, on a per-pixel basis, controlling exposure time of each of the pixels on the basis of a monotonically rising convex function of the associated photocurrent of each of the pixel.

Abstract: A packet co-processing system for improving the performance of an Application Specific Integrated Circuit (ASIC), including: a set of N search engines, logically disposed so as to form a chain of search engines, including: (a) a first search engine for connecting to the ASIC; (b) a terminal search engine, and (c) a set of N?2 intermediate search engines, logically disposed between the first search engine and the terminal search engine (N=2), and wherein each particular search engine includes: (i) an input selector including a parsing unit configured to: (A) select a particular set of fields containing at least a portion of at least one field from a larger, first set of fields submitted to the particular search engine, and (B) produce a Synthesized Key using data from the particular set of fields; (ii) search logic configured to: (A) search a memory, in response to the Synthesized Key, for a key entry matching the Synthesized Key, and (B) retrieve associated data corresponding to the Synthesized Key, and (iii)

Abstract: An associative search engine (ASE) including: (a) a search engine manager (SEM), disposed within a chip, including: (i) processing logic; (b) an external memory system, disposed outside of the chip, including: (i) a plurality of memory storage units, each memory storage unit of the memory storage units having at least a first array for storing a plurality of key entries; (c) at least a second array for storing a plurality of associated data entries, the data entries being associated with the key entries, and (d) an interface for data interfacing between the external memory system and the SEM, wherein the processing logic is designed and configured to search within each of the memory storage units, in response to an input key, so as to determine if the input key matches a particular key entry, and wherein the key entries are stored in the memory storage units as logical two-dimensional arrays (TDAs) arranged for a search tree having a plurality of levels, so as to provide an increased rate of the data retrieva

Abstract: A method and system for storing arranged data in a memory, the system including: (a) a plurality of random access memories, each random access memory (RAM) of the plurality including: (i) a first array of cells, the first array having at least two dimensions and having rows and columns, the first array designed and configured to contain a plurality of key entries, each of the cells having a unique address including a row index and a column index, each of the key entries for matching with an input key, and (b) a processor designed and configured to search the plurality of key entries for a match, in response to the input key, the plurality of RAMs designed and configured such that: (i) at least one row in a second of the RAMs has a row index that is identical to a row index in a first of the RAMs, and (ii) the key entries are arranged within each of the plurality of RAMs in monotonic order.

Abstract: Method and device for arranging and storing data in a memory and for extracting the data from the memory in response to an input key, the method including the steps of: (a) providing at least a first array having at least two dimensions, the first array having rows and columns, the first array for storing a plurality of key entries; (b) providing at least a second array having at least two dimensions, the second array having rows and columns, the second array for storing a plurality of data entries, each of the data entries being associated with a particular one of the key entries; (c) arranging the key entries in monotonic order, and (d) identifying a single row among the rows of the first array as a sole row that may contain a particular stored key.

Abstract: A computer-implemented method for flexibly storing data in a database so as to allow facile updating and maintenance of the database, including the steps of: (a) providing a first array having rows and columns for storing a first plurality of key entries; (b) arranging the key entries within each of the rows in a monotonic order; (c) providing a second array for storing a second plurality of key entries having rows and at least one column, such that the first and second arrays form a hierarchical structure, wherein the second plurality of entries represents a higher level of the hierarchical structure with respect to the first plurality of entries; (d) identifying an update position for performing a database update operation, and (e) performing the update operation by rearranging a portion of the first plurality of entries.

Abstract: A device for, and method of, storing data in a memory, and for extracting the data therefrom based on a multi-dimensional input (MDI) key, the device including a first and at least a second associative search engine (ASE), each including: (i) a memory having: (A) a first array of cells containing a field of entries, each of the cells being accessible via an input key including a string corresponding to at least a portion of the MDI key, and (B) a second array of cells having a plurality of associated data entries, each of the associated data entries being associated with a particular one of the entries in the first array, and (ii) control logic for operatively connecting the first and the second ASE, the control logic for processing at least a portion of the entries in the first array from each ASE, in response to the input key, so as to determine a match between the input key and an entry of said entries in said field; the control logic for producing a result pertaining to an associated data entry based on t

Abstract: A system and method for storing arranged data in a memory, and for extracting the data therefrom, the system including: (a) a random access memory (RAM) including: (i) a first array of cells, the first array having at least two dimensions and having rows and columns, the first array designed and configured to contain a plurality of at least two kinds of key entries, each of the cells having a unique address and being accessible via an input key, each of the kinds of key entries being arranged in monotonic order, and (ii) a second array of cells, the second array having at least two dimensions and having rows and columns, the second array having a plurality of data entries, each of the data entries being associated with a particular one of the key entries, and (b) processing means designed and configured to search, in response to the input key, the plurality of key entries so as to identify a match.

Abstract: A packet co-processing system for improving the performance of an Application Specific Integrated Circuit (ASIC), including: a set of N search engines, logically disposed so as to form a chain of search engines, including: (a) a first search engine for connecting to the ASIC; (b) a terminal search engine, and (c) a set of N?2 intermediate search engines, logically disposed between the first search engine and the terminal search engine (N=2), and wherein each particular search engine includes: (i) an input selector including a parsing unit configured to: (A) select a particular set of fields containing at least a portion of at least one field from a larger, first set of fields submitted to the particular search engine, and (B) produce a Synthesized Key using data from the particular set of fields; (ii) search logic configured to: (A) search a memory, in response to the Synthesized Key, for a key entry matching the Synthesized Key, and (B) retrieve associated data corresponding to the Synthesized Key, and (iii)

Abstract: A method for arranging and storing data in a memory and for extracting the data from the memory in response to an input key, including the steps of (a) providing at least a first array having at least two dimensions, the first array consisting of rows and columns, the first array for storing a plurality of range boundary information; (b) providing at least a second array having at least two dimensions, the second array consisting of rows and columns, the second array for storing a plurality of associated data entries; (c) processing sets of range information to produce, for each of the sets: (i) range boundary information including at least one range-boundary value, the range boundary information being associated with a particular one of the associated data entries, and (ii) range validity information, and (d) storing the range boundary information within the first array.

Abstract: A multiple-stage comparator for comparing N-bit binary numbers, including: (a) a device for splitting each of the N-bit (N≧1) binary numbers into segments, and (b) computer implemented comparator units having: (i) at least two inputs containing information on a first segment, (ii) a processor having processing logic for examining and evaluating the information, so as to provide comparative information on at least the first segment, the comparative information including at least one result selected from the group consisting of a produced equality result and a produced inequality result, and (iii) at least one output containing the result, wherein a first plurality of the comparator units is logically disposed in parallel with respect to one another, and wherein at least a second plurality of the comparator units is logically disposed in series with respect to one another.

Abstract: An image sensor array including a first plurality of unit cells coupled to a first sense amplifier, and a second plurality of unit cells coupled to a second sense amplifier, where the first plurality and the second plurality are substantially electrically isolated from each other.

Abstract: A multi-cell cluster which includes a plurality of light-detecting unit cells and a single charge-integration and readout circuitry. Typically, each of the cells produces charge representative of the detected light. The circuit may be shared by the plurality of unit cells, and used to read-out the charge in real-time. The cluster may also include a switch associated with each unit cell, such that each switch connects its associated unit cell to the circuit. The switch may also be controlled in a time-multiplexing manner. Each unit cell may include a photodetector, a photodiode, or a photogate. The circuit may include a shared storage device, a shared reset circuit, or a readout circuit. Typically, the shared storage device may be for accumulating the charge in the focal plane. The here-above described apparatus facilitates either static or dynamic, either local or global image resolution/sensitivity tradeoffs.

Abstract: A method and device for arranging and storing data in a memory and for extracting the data from the memory in response to an input key, the method including the steps of: (a) providing a device including: (i) a memory having a plurality of module pairs, each of the module pairs having: (A) a key module including a first array of cells, the first array having at least two dimensions and having rows and columns, the first array containing a plurality of keys, each of the cells having a unique address and being accessible via an input key, the keys within each of the key modules being arranged in monotonic order, and (B) an associated data module including a second array of cells, the second array having at least two dimensions and having rows and columns, the second array having a plurality of data entries, associated with the keys, wherein the memory is designed and configured such that each of the data entries is associated with a particular one of the keys, and (ii) processing means, and (b) performing a pro

Abstract: An associative search engine (ASE) including: (a) a search engine manager (SEM), disposed within a chip, including: (i) processing logic; (b) an external memory system, disposed outside of the chip, including: (i) a plurality of memory storage units, each memory storage unit of the memory storage units having at least a first array for storing a plurality of key entries; (c) at least a second array for storing a plurality of associated data entries, the data entries being associated with the key entries, and (d) an interface for data interfacing between the external memory system and the SEM, wherein the processing logic is designed and configured to search within each of the memory storage units, in response to an input key, so as to determine if the input key matches a particular key entry, and wherein the key entries are stored in the memory storage units as logical two-dimensional arrays (TDAs) arranged for a search tree having a plurality of levels, so as to provide an increased rate of the data retrieva

Abstract: Method and device for arranging and storing data in a memory and for extracting the data from the memory in response to an input key, the method including the steps of: (a) providing at least a first array having at least two dimensions, the first array having rows and columns, the first array for storing a plurality of key entries; (b) providing at least a second array having at least two dimensions, the second array having rows and columns, the second array for storing a plurality of data entries, each of the data entries being associated with a particular one of the key entries; (c) arranging the key entries in monotonic order, and (d) identifying a single row among the rows of the first array as a sole row that may contain a particular stored key.

Abstract: A method for compressing the dynamic range of an image sensor (202) including a multiplicity of pixels. The method includes the steps of exposing each of the pixels to light and producing an associated photocurrent per pixel, representative of the light exposure. Then, on a per-pixel basis, controlling exposure time of each of the pixels on the basis of a monotonically rising convex function of the associated photocurrent of each of the pixel.

Abstract: A multi-cell cluster which includes a plurality of light-detecting unit cells and a single charge-integration and readout circuitry. Typically, each of the cells produces charge representative of the detected light. The circuit may be shared by the plurality of unit cells, and used to read-out the charge in real-time. The cluster may also Include a switch associated with each unit cell, such that each switch connects its associated unit cell to the circuit. The switch may also be controlled in a time-multiplexing manner. Each unit cell may include a photodetector, a photodiode, or a photogate. The circuit may include a shared storage device, a shared reset circuit, or a readout circuit. Typically, the shared storage device may be for accumulating the charge in the focal plane. The here-above described apparatus facilitates either static or dynamic, either local or global image resolution/sensitivity tradeoffs.