Abstract: A method of encoding generalized concatenated error-correcting codes includes providing a parity Matrix {tilde over (H)}j of a j-th layer code and predefined syndrome {tilde over (s)} of length n?{tilde over (k)}j, where the first n?kl coordinates are zero, n is a length of a codeword c of a first layer BCH code Cl of dimension {tilde over (k)}j, codeword c satisfies {tilde over (H)}jc={tilde over (s)}, a first layer code includes only a BCH code, and each subsequent layer includes a Reed-Solomon (RS) stage followed by a BCH code; finding a square matrix Rj of dimension (n?{tilde over (k)}j)(n?{tilde over (k)}j) such that Rj{tilde over (H)}j=(A|I), where A is an arbitrary matrix, Rj=(Qj|Tj), where Q has n?kl columns and Tj has k1?{tilde over (k)} columns; finding a vector c=(a b) where a is a vector of length {tilde over (k)}j and b is a vector of length n?{tilde over (k)}j; and solving ( A | I ) ? ( a b ) = ( Q j | T j ) ? s ~ = T j ? s where a=0 and b=Tjs, and cod

Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

Abstract: A method of storing survivor data generated while decoding channel polarization codes in a memory module includes setting a list size that corresponds to a number of decoder units used to decode the channel polarization codes, inputting a stream of input bits to the decoder units, and sequentially decoding the input bits. Each input bit is decoded using all previous input bits decoded before the each input bit. The method further includes selecting a plurality of survivor bits from among the decoded input bits, and storing the selected survivor bits in the memory module in a binary tree configuration. The number of edges in each level of the binary tree configuration does not exceed the list size.

Abstract: A method for generating a binary GTP codeword, comprised of N structure stages and each stage comprises at least one BCH codeword with error correction capability greater than a prior stage and smaller than a next stage, includes: receiving a syndrome vector s of a new stage 0 binary BCH codeword y over a field GF(2m) that comprises ?t syndromes of length m bits, wherein the syndrome vector s comprises l-th Reed-Solomon (RS) symbols of ?t RS codewords whose information symbols are delta syndromes of all BCH codewords from stage 0 until stage n?1; and multiplying s by a right submatrix ? of a matrix U, wherein U is an inverse of a parity matrix of an BCH code defined by tn, wherein the new binary BCH codeword is y=?·s.

Abstract: A method of operating a storage device including a nonvolatile memory can be provided by receiving, from a host, address change information including changing logical addresses for data to be stored in the nonvolatile memory. Physical addresses can be sequentially allocated to the changing logical addresses included in the address change information to provide a first journal. A portion of at least one physical address allocated to the changing logical addresses can be removed to provide a second journal and the second journal can be stored in the nonvolatile memory.

Abstract: A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

Abstract: A method of correcting values errantly attributed to bits of error correction code (ECC) blocks during a read operation. The method includes, upon determining that an error exists in the jth bit of one or more of the ECC blocks: 1) retrieving an estimate of the voltage value stored by the nonvolatile memory cell corresponding to the jth bit of each of the ECC blocks having errant data; 2) identifying, among the voltage value estimates retrieved in operation (1), an ECC block whose corresponding voltage value estimate retrieved in operation (1) is closest to the voltage value of a decision boundary for determining whether to assign a bit value of “0” or “1” to the jth bit of the ECC blocks; and 3) inverting the value of the jth bit of the ECC block identified in operation (2).

Abstract: A memory system includes a memory controller; and a memory device, the memory device including a memory cell array, the memory cell array including least a first memory page having a plurality of memory cells storing a plurality of stored bits, the memory controller being such that, the memory controller performs a first hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits, and if the memory controller determines to change a value of one of a first group of bits, from among the plurality of read bits, the memory controller selects one of the first group of bits based on log likelihood ratio (LLR) values corresponding, respectively, to each of the first group of bits, and changes the value of the selected bit.

Abstract: A decoding method for an iterative message-passing based decoder, such as a low-density parity-check (LDPC) decoder, includes calculating syndrome information for a received word, and initializing variable nodes based on the received word. Each received bit of the received word may be represented by a Likelihood-Ratio (LR) or Log-Likelihood-Ratio (LLR) at a respective variable node. Further, the method includes iteratively updating check nodes, and updating the LRs of variable nodes using the syndrome information, determining an error vector from the LRs of the variable nodes, and determining a transmitted word, corresponding to the received word, by subtracting the error vector from the received word. The syndrome information is calculated based upon a parity check matrix.

Abstract: Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern.

Abstract: A memory controller of a memory system, the memory system including the memory controller and a memory device, includes a processor configured to receive write data an control the memory controller; and an encoder, the processor being configured to, receive write data, read previously programmed data from a first memory page of a memory cell array of the memory device, and control the encoder to generate encoded data by encoding the write data using stuck bit code (SBC), based on the read previously programmed data, the previously programmed data being data that has been programmed into the first memory page of the memory cell array and has not been erased; the processor being configured to write the encoded data to the first memory page without erasing the first memory page.

Abstract: A method for protecting encoded data from algebraic manipulation includes receiving a data word s?Kd to be protected, randomly selecting two integers a ?{0, . . . , q?1} and b ?{0, . . . , ?q?1}, finding a point (?, ?) on a Hermitian curve over a field Fq that corresponds to the randomly selected integers (a, b) from a mapping (a, b)(?, ?)=(ua, ua?q+1z+vb), where u a := { 0 if ? ? a = 0 , ? 1 a - 1 otherwise , ? V b := { 0 if ? ? b = 0 , ? 2 b - 1 otherwise , and z is an element of the field Fq of unit trace, and where ?1 is a fixed primitive element of the field Fq and ?2 is a primitive element of a field F?q?Fq, and calculating a sum fs(?, ?)=?id+1?jd+1+?k=1d?ik?kjk for a set of d+1 integers pairs I ={(ik,jk)}k=1d+1, where the encoded word is a triple (s, (?, ?),fs(?, ?)).

Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells. In a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

Abstract: A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.

Abstract: A method for protecting encoded data from algebraic manipulation includes receiving a data word s?Kd to be protected, randomly selecting two integers a?{0, . . . , q?1} and b?{0, . . . , ?q?1}, finding a point (?, ?) on a Hermitian curve over a field Fq that corresponds to the randomly selected integers (a, b) from a mapping (a, b)(?, ?)=(ua, ua?q+1z+vb), where u a := { 0 if ? ? a = 0 , ? 1 a - 1 otherwise , ? ? V b := { 0 if ? ? b = 0 , ? 2 b - 1 otherwise , and z is an element of the field Fq of unit trace, and where ?1 is a fixed primitive element of the field Fq and ?2 is a primitive element of a field F?q?Fq, and calculating a sum fs(?, ?)=?id+1?jd+1+?k=1d?ik?kjk or a set of d+1 integers pairs I={(ik,jk)}k=1d+1, where the encoded word is a triple (s, (?, ?),fs(?, ?)).

Abstract: Methods of driving a memory include erasing a plurality of memory cells of a memory device, testing whether the memory cells have been erased, and programming the memory cells without erasing the memory cells again if more than a predetermined percentage of the memory cells, but less than all of the memory cells, were successfully erased.

Abstract: A method of operating a memory device includes programming a first data signal to a first memory cell, attempting to program a second data signal to the first memory cell in a state where the first memory cell is not erased, and marking the first memory cell as blank upon failing to program the second data signal to the first memory cell.

Abstract: Example embodiments disclose methods and apparatuses for encoding and decoding data in a memory system. In an encoding method according to an example embodiment of inventive concepts, a codeword is generated based on a combination of data to be stored and auxiliary data according to stuck cells and an encoding matrix based on information, regarding coordinates of the stuck cells and values of the stuck cells. The generated codeword includes data corresponding to the values of the stuck cells at addresses corresponding to the coordinates of the stuck cells, in a decoding method according to an example embodiment of inventive concepts, data may be generated by multiplying an inverse matrix of the encoding matrix used for encoding by the codeword.

Abstract: Provided are a coding/decoding method for use in a multi-level memory system. The coding method includes searching for a set of symbols that may generate a forbidden pattern that is set initially from an input data stream, and sticking at least one bit included in the searched set of the symbols that may generate the forbidden pattern so as not to generate the forbidden pattern.

Abstract: A low-density parity-check (LDPC) decoding method includes exchanging messages between check nodes and variable nodes based on scheduling information representing an order of exchanging messages between the check nodes and the variable nodes for an LDPC decoding, and performing the LDPC decoding based on the exchanged messages, wherein the scheduling information is determined by manipulating at least one of an order of the check nodes and an order of the variable nodes in an LDPC bipartite graph.