Abstract: Compositions, systems, and methods for reducing electrosensation and/or skin irritation in response to the application of alternating electric fields to a skin of a subject are disclosed. The compositions, systems, and methods involve administration of at least one composition comprising at least one localized numbing agent to the subject followed by application of an alternating electric field to the subject.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for matching items with resources, such as, but not limited to packet processing contexts, output links, memory, storage, specialized hardware or software, compute cycles, or any other entity. One implementation includes means for maintaining distribution groups of items, means for maintaining differently aged resources queues, and means for matching resources identified as being at the head of the plurality of differently aged resources queues and as being primarily and secondarily associated with said distribution groups based on a set of predetermined criteria.

Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques.

Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, a packet of multiple streams of packets is received. A subset of bytes of the packet are distributed to the next packet processor determined based on a distribution pattern. The subset of the packet is processed to generate a modified subset, which is gathered in turn based on the distribution pattern; and a modified packet including the modified subset is forwarded.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for matching items with resources, such as, but not limited to packet processing contexts, output links, memory, storage, specialized hardware or software, compute cycles, or any other entity. One implementation includes means for maintaining distribution groups of items, means for maintaining differently aged resources queues, and means for matching resources identified as being at the head of the plurality of differently aged resources queues and as being primarily and secondarily associated with said distribution groups based on a set of predetermined criteria.

Abstract: A method of automatically activating a clock master circuit in a stack of repeaters includes selectively connecting a first on pin in a first repeater to a voltage source when the first repeater is powered on. The first on pin is connected to a power state output pin in a second repeater, wherein the power state output pin is configured to be connected to ground when the second repeater is powered on. A clock master circuit is enabled based on the voltage on the first on pin.

Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.

Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.

Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.

Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, a packet of multiple streams of packets is received. A subset of bytes of the packet are distributed to the next packet processor determined based on a distribution pattern. The subset of the packet is processed to generate a modified subset, which is gathered in turn based on the distribution pattern; and a modified packet including the modified subset is forwarded.

Abstract: Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to individual packet processors and gathering the processed packet or subsets and forwarding the resultant modified or otherwise processed packets, accessing packet processing resources across a shared resource network, accessing packet processing resources using direct memory access techniques, and/or storing one overlapping portion of a packet in a global packet memory while providing a second overlapping portion to a packet processor. In one implementation, the processing of the packet includes accessing one or more processing resources across a resource network shared by multiple packet processing engines. In one implementation, a global packet memory is one of these resources. In one implementation, these resources are accessed using direct memory access (DMA) techniques.

Abstract: An automatically activated bus termination circuit in a repeater that is suitable for inclusion in a repeater stack including an end unit determination circuit is described. The end unit determination circuit includes a local input connector having an input sense pin. The input sense pin is configured to be connected to an input sense potential when the local input connector is connected to a remote output connector. A local output connector has an output sense pin. The output sense pin is configured to be connected to an output sense potential when the local output connector is connected to a remote input connector. A bus termination circuit is configured to be active when either the input sense pin is not connected to the input sense potential or the output sense pin is not connected to the output sense potential.

Abstract: Provided is a system which automatically determines and assigns an appropriate address for each chip in repeater system. All the ASICs in a system are chained together on a serial data ring for address allocation purposes. A “First On” ASIC in a system initializes the chip address map, assigns itself the first address. The First On ASIC then updates the address map by setting the next address and sends it down the chain to the next ASIC in the system. The second ASIC allocates the incoming address to itself, sets the address for the next ASIC, and passes the address signal on. The process repeats itself until the last ASIC in the chain has an address allocated. The last ASIC the notifies the First On ASIC of its address to close the loop.

Abstract: Provided is a synchronous stack bus repeater system for a computer network. The system includes a plurality of stacked repeaters, a stack bus linking the repeaters, and a single clock to which the plurality of repeaters is synchronized. The synchronization of the stack bus eliminates several time-consuming communications required between devices operating with different clocks on an asynchronous bus and makes it possible to satisfy the 46 bit time repeater maximum latency required of a Class II repeater according to the IEEE 802.3 standard.

Abstract: Provided is a system which automatically determines and assigns an appropriate address for each chip in a repeater system. All the ASICs in a system are chained together on a serial data ring for address allocation purposes. A "First On" ASIC in a system initializes the chip address map, and assigns itself the first address. The First On ASIC then updates the address map by setting the next address and sends it down the chain to the next ASIC in the system. The second ASIC allocates the incoming address to itself, sets the address for the next ASIC, and passes the address signal on. The process repeats itself until the last ASIC in the chain has an address allocated. The last ASIC then notifies the First On ASIC of its address to close the loop.

Abstract: An apparatus for automatically activating a clock master circuit in a stack of Fast Ethernet repeaters includes a first stackable Fast Ethernet repeater is disclosed. The first stackable Fast Ethernet repeater includes a first on pin having a first on pin logical state. The first on pin logical state is indicative of whether or not the first stackable Fast Ethernet repeater is configured in the stack of Fast Ethernet repeaters so that no other Fast Ethernet repeater occupying a position in the Fast Ethernet repeater stack that is before the position of the first Fast Ethernet repeater is powered on. A weak pull up voltage source is connected to the first on pin. The weak pull up voltage is derived from a switched power supply in the Fast Ethernet repeater so that when the Fast Ethernet repeater is powered on, the weak pull up voltage is present and when the Fast Ethernet repeater is powered off, the weak pull up voltage is not present.

Abstract: An automatically activated bus termination circuit in a repeater which is suitable for inclusion in a repeater stack including an end unit determination circuit. The end unit determination circuit includes a local input connector having an input sense pin. The input sense pin is configured to be connected to an input sense potential when the local input connector is connected to a remote output connector having an output sense pin. The output sense pin is configured to be connected to an output sense potential when the local output connector is connected to a remote input connector. The bus termination circuit is configured to be active when either the input sense pin is not connected to the input sense potential or the output sense pin is not connected to the output sense potential.