Abstract: A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.

Abstract: In an embodiment, the design flow is modified to avoid the flattening process but still accurately annotate the transistors with stress parameters. The location-based stress parameters may be generated, but may not be provided to the LVS tool. Instead, a hierarchical LVS process may be performed, black-boxing lower level blocks that already have stress parameter assignments, preserving hierarchy, etc. The output database from LVS thus includes a cross reference between layout devices and schematic devices, as well as locations of the schematic devices. The database may then be queried for the transistors in the non-flattened design, and the stress parameters may be assigned to the transistors based on the location-based stress parameters. In this fashion the stress parameters may be assigned to the desired transistors, permitting annotation of these parameters into the schematics, without flattening the design and doing unnecessary work on blocks to be skipped.

Abstract: A method includes defining an array including a plurality of unit cells, receiving unit cell density parameters in a computing apparatus, and defining a plurality of sub-arrays of unit cells using the computing apparatus. The computing apparatus defines density features disposed between adjacent sub-arrays. The computing apparatus generates density feature density parameters based on the unit cell density parameters and at least one density limit.