Abstract: This application discloses a computing system configured to crop a layout design for an electronic device implemented with a layered interconnect, place a termination structure corresponding to a resistive sheet or a set of resistive components on an artificial boundary corresponding to an edge in the cropped portion of the layout design, and generate an electrical model of a signaling net in the cropped portion of the layout design by generating mesh elements on a surface area of the cropped portion of the layout design including the termination structure and utilizing a field solver implementing a Boundary Element Method based analysis to solve integral forms of Maxwell's equations corresponding to the mesh elements. The electrical model of the signaling net in the cropped portion of the layout design can include a set of scattering parameters for the signaling net in the cropped portion of the layout design.