Patents by Inventor Moslem Didehban

Moslem Didehban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230115158
    Abstract: A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.
    Type: Application
    Filed: September 19, 2022
    Publication date: April 13, 2023
    Applicant: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
  • Patent number: 11449380
    Abstract: A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 20, 2022
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
  • Patent number: 10997027
    Abstract: Systems and methods for implementing a lightweight checkpoint technique for resilience against soft errors are disclosed. The technique provides effective, safe, and timely soft error detection and recovery using software. In an exemplary aspect, resilience against data flow errors and control flow errors is provided in critical or mixed-critical applications in each basic block or at critical basic blocks. Verified register preservation is provided at each basic block, along with memory preservation checkpoints. In this manner, soft errors are quickly detected and addressed. The register and memory preservation further allows for safe re-execution from recoverable soft errors. Control flow errors can also be detected at the beginning and/or end of each basic block.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 4, 2021
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Moslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava
  • Publication number: 20190378542
    Abstract: A method for detecting and recovery from a soft error in a computing device is provided. In examples discussed herein, the method can be performed to detect soft errors that may occur during execution of a predefined critical instruction(s) and/or has been propagated in the computing device prior to the execution of the predefined critical instruction(s). Specifically, a software compiler may be used to embed an error detector block(s) after the predefined critical instruction(s). In this regard, the error detector block(s) can be executed after the predefined critical instruction(s) to detect the soft error. Accordingly, it may be possible to invoke a diagnosis routine to determine severity of the detected soft error and take appropriate action against the detected soft error. As such, it may be possible to protect the execution of the predefined critical instruction(s) concurrent to eliminating vulnerable voting intervals and reducing soft error detection overhead.
    Type: Application
    Filed: May 23, 2019
    Publication date: December 12, 2019
    Applicant: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
  • Publication number: 20190196912
    Abstract: Systems and methods for implementing a lightweight checkpoint technique for resilience against soft errors are disclosed. The technique provides effective, safe, and timely soft error detection and recovery using software. In an exemplary aspect, resilience against data flow errors and control flow errors is provided in critical or mixed-critical applications in each basic block or at critical basic blocks. Verified register preservation is provided at each basic block, along with memory preservation checkpoints. In this manner, soft errors are quickly detected and addressed. The register and memory preservation further allows for safe re-execution from recoverable soft errors. Control flow errors can also be detected at the beginning and/or end of each basic block.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Applicant: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Moslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava
  • Patent number: 10296312
    Abstract: Methods, apparatuses, systems, and implementations of a zero silent data corruption (ZDC) compiler technique are disclosed. The ZDC technique may use an effective instruction duplication approach to protect programs from soft errors. The ZDC may also provide an effective control flow checking mechanism to detect most control flow errors. The ZDC technique may provide a failure percentage close to zero while incurring a lower performance overhead than prior art systems. The ZDC may also be effectively applied in a multi-thread environment.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 21, 2019
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Aviral Shrivastava, Moslem Didehban
  • Publication number: 20170337047
    Abstract: Methods, apparatuses, systems, and implementations of a zero silent data corruption (ZDC) compiler technique are disclosed. The ZDC technique may use an effective instruction duplication approach to protect programs from soft errors. The ZDC may also provide an effective control flow checking mechanism to detect most control flow errors. The ZDC technique may provide a failure percentage close to zero while incurring a lower performance overhead than prior art systems. The ZDC may also be effectively applied in a multi-thread environment.
    Type: Application
    Filed: May 17, 2017
    Publication date: November 23, 2017
    Applicant: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Aviral Shrivastava, Moslem Didehban