Patents by Inventor Mostafa A. Aghazadeh

Mostafa A. Aghazadeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240006358
    Abstract: Bonding pedestals on substrates, and their manufacture, for direct bonding integrated circuit (IC) dies onto substrates. The electrical interconnections of one or more IC dies and a substrate are bonded together with the IC dies on and overhanging the pedestals. A bonding pedestal may be formed by etching down the substrate around the interconnections. A system may include one or more such pedestals above and adjacent a recessed surface on a substrate with IC dies overhanging the pedestals. Such a system may be coupled to a host component, such as a board, and a power supply via the host component.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Zhihua Zou, Omkar Karhade, Botao Zhang, Julia Chiu, Vivek Chidambaram, Yi Shi, Mohit Bhatia, Mostafa Aghazadeh
  • Patent number: 11679407
    Abstract: To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM?0.01-0.025° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Kyle Jordan Arrington, Joseph Blaine Petrini, Aaron McCann, Shankar Devasenathipathy, James Christopher Matayabas, Jr., Mostafa Aghazadeh, Jerrod Peterson
  • Publication number: 20210101175
    Abstract: To address technical problems facing silicon transient thermal management, a thermal interface material (TIM) may be used to provide improved thermal conduction. The TIM may include a liquid metal (LM) TIM, which may provide a significant reduction in thermal resistance, such as a thermal resistance RTIM?0.01-0.025 ° C.-cm2/W. The LM TIM may be applied using a presoaked applicator, such as an open-cell polyurethane foam applicator that has been presoaked in a controlled amount of LM TIM. This LM presoaked applicator is then used to apply the LM TIM to one or more target thermal surfaces, thereby providing thermal and mechanical coupling between the LM TIM and the thermal surface. The resulting thermal surface and thermally conductive LM TIM may be used to improve thermal conduction for various silicon-based devices, including various high-power, high-performance system-on-chip (SoC) packages, such as may be used in portable consumer products.
    Type: Application
    Filed: June 26, 2020
    Publication date: April 8, 2021
    Inventors: Kyle Jordan Arrington, Joseph Blaine Petrini, Aaron McCann, Shankar Devasenathipathy, James Christopher Matayabas, JR., Mostafa Aghazadeh, Jerrod Peterson
  • Patent number: 5838542
    Abstract: The processor card assembly of the present invention includes a processor card, a metallic plate and a back cover. The processor card includes a circuit board having a processor mounted thereto. The circuit board includes a first and a second plurality of fastening features. The metallic plate has a third and a fourth plurality of fastening features. The third plurality of fastening features cooperate with the first plurality of fastening features for physically attaching and thermally coupling the processor to the metallic plate, to serve as a base for further thermally coupling the processor to a heat sink.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: November 17, 1998
    Assignee: Intel Corporation
    Inventors: Darul J. Nelson, James V. Noval, Ricardo E. Suarez, Mostafa A. Aghazadeh
  • Patent number: 5808875
    Abstract: An integrated circuit package that has no internal routing or vias within the substrate of the package. The package includes a substrate that has a plurality of bond pads and connecting contact pads located on an outer first surface of the substrate. An integrated circuit is mounted to the first surface and coupled to the bond pads. Mounted to the substrate is a solder rack which contains a plurality of contacts that couple the contact pads to an external printed circuit board.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: September 15, 1998
    Assignee: Intel Corporation
    Inventors: John Francis McMahon, Mostafa Aghazadeh, Frank Kolman
  • Patent number: 5621245
    Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt-to-3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5 V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip. VSS ground on board pins are connected in common to both the ground terminal of the voltage regulator and the VSS pads of the chip.
    Type: Grant
    Filed: October 31, 1996
    Date of Patent: April 15, 1997
    Assignee: Intel Corporation
    Inventors: Willy Agatstein, Mostafa Aghazadeh, Chia-pin Chiu, Amar Ghori, James R. Neal, Gregory Turturio
  • Patent number: 5621613
    Abstract: A heat transfer apparatus providing thermal coupling between a first and a second hinged member. The first hinged member is a first computer housing member, and the second hinged member is a second computer housing member. The first and the second computer housing members are rotatably attached allowing pivotal motion along an axis substantially parallel to the first edge. A first embodiment has a spiraled heat transfer element with a inner edge thermally coupled to a heat conductive mounting element mounted along the first edge of the first computer housing member. The spiraled heat transfer element forms at least one turn around the heat conductive mounting element and has outer edge affixed to the second computer housing member. A second embodiment provides heat transfer between the first and second computer housing members through the gudgeon and the pintle of the hinge.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: April 15, 1997
    Assignee: Intel Corporation
    Inventors: Kevin Haley, Mostafa Aghazadeh, Hong Xie
  • Patent number: 5556811
    Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt- to- 3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: September 17, 1996
    Assignee: Intel Corporation
    Inventors: Willy Agatstein, Mostafa Aghazadeh, Chia-pin Chiu, Amar Ghori, James R. Neal, Gregory Turturio
  • Patent number: 5513070
    Abstract: An improved heat dissipation device particularly suited for removing heat from a surface mounted integrated circuit component coupled to a printed circuit board in a portable computer. Vias, which are at least partially filled with a heat conductive material, improve heat transfer between a component and a heat conductive block mounted on opposite surfaces of the circuit board. A first section near one end of the heat pipe is attached to the heat conductive block in a channel formed receptive to the heat pipe. A second section of the heat pipe including the second end is attached to a metal plate which is affixed beneath the keyboard. Heat from the component flows through the vias to the block and is transferred by the heat pipe to the metal plate where it is dissipated.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: April 30, 1996
    Assignee: Intel Corporation
    Inventors: Hong Xie, Mostafa Aghazadeh, Gregory Turturro, Chia-Pin Chiu
  • Patent number: 5289337
    Abstract: A converging design multi-chip module having semiconductor chips connected to a substrate recessed into a cavity of the MCM package body, the chips being interconnected using flip chip and control collapse chip connection, wherein a metal heatspreader plate is adapted to engage the backside of the chips and is held in place by an attachment ring welded to the package body. Alternatively, the heatspreader plate can be glued directly to the backside of the chips using a high thermal conductivity and low modulus cement. One or more electrically passive thermal shunt chips are disposed between the substrate and the heatspreader plate for additional heat conduction. In a preferred embodiment, the attachment ring is made from KOVAR.RTM. and has a thermal coefficient of expansion that is about the same as that of the package body. Thermal grease is interposed between the heatspreader plate and the semiconductor chips for improved heat transfer.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: February 22, 1994
    Assignee: Intel Corporation
    Inventors: Mostafa Aghazadeh, Mark Palmer