Patents by Inventor Mostafa EL GAMAL
Mostafa EL GAMAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11735252Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.Type: GrantFiled: June 25, 2021Date of Patent: August 22, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Mostafa El Gamal, Niranjay Ravindran, James Fitzpatrick
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Patent number: 11636039Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.Type: GrantFiled: May 17, 2022Date of Patent: April 25, 2023Assignee: Western Digital Technologies, Inc.Inventors: Bernie Rub, Mostafa El Gamal, Niranjay Ravindran, Richard David Barndt, Henry Chin, Ravi J. Kumar, James Fitzpatrick
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Patent number: 11562787Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.Type: GrantFiled: June 23, 2021Date of Patent: January 24, 2023Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
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Publication number: 20220283950Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.Type: ApplicationFiled: May 17, 2022Publication date: September 8, 2022Applicant: Western Digital Technologies, Inc.Inventors: Bernie RUB, Mostafa EL GAMAL, Niranjay RAVINDRAN, Richard David BARNDT, Henry CHIN, Ravi J. KUMAR, James FITZPATRICK
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Patent number: 11372765Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.Type: GrantFiled: June 18, 2020Date of Patent: June 28, 2022Assignee: Western Digital Technologies, Inc.Inventors: Bernie Rub, Mostafa El Gamal, Niranjay Ravindran, Richard David Barndt, Henry Chin, Ravi J. Kumar, James Fitzpatrick
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Patent number: 11256567Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.Type: GrantFiled: June 22, 2020Date of Patent: February 22, 2022Assignee: SanDisk Technologies LLCInventors: Mostafa El Gamal, James Fitzpatrick
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Publication number: 20210327504Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.Type: ApplicationFiled: June 25, 2021Publication date: October 21, 2021Inventors: Mostafa EL GAMAL, Niranjay RAVINDRAN, James FITZPATRICK
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Publication number: 20210319828Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.Type: ApplicationFiled: June 23, 2021Publication date: October 14, 2021Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
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Patent number: 11107522Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.Type: GrantFiled: June 25, 2020Date of Patent: August 31, 2021Assignee: Western Digital Technologies, Inc.Inventors: Mostafa El Gamal, Niranjay Ravindran, James Fitzpatrick
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Patent number: 11087836Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.Type: GrantFiled: December 18, 2020Date of Patent: August 10, 2021Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
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Publication number: 20210104275Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.Type: ApplicationFiled: December 18, 2020Publication date: April 8, 2021Inventors: Richard David BARNDT, Bernardo RUB, Mostafa EL GAMAL
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Patent number: 10878896Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.Type: GrantFiled: July 22, 2020Date of Patent: December 29, 2020Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
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Publication number: 20200350007Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Richard David BARNDT, Bernardo RUB, Mostafa EL GAMAL
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Publication number: 20200327933Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.Type: ApplicationFiled: June 25, 2020Publication date: October 15, 2020Inventors: Mostafa EL GAMAL, Niranjay RAVINDRAN, James FITZPATRICK
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Publication number: 20200319965Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Applicant: SanDisk Technologies LLCInventors: Mostafa El Gamal, Jim Fitzpatrick
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Publication number: 20200320009Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Inventors: Bernie RUB, Mostafa EL GAMAL, Niranjay RAVINDRAN, Richard David BARNDT, Henry CHIN, Ravi J. KUMAR, James FITZPATRICK
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Patent number: 10748606Abstract: Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.Type: GrantFiled: December 14, 2018Date of Patent: August 18, 2020Assignee: Western Digital Technologies, Inc.Inventors: Richard David Barndt, Bernardo Rub, Mostafa El Gamal
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Patent number: 10733047Abstract: An apparatus includes memory cells programmed to one of a plurality of data states, wherein the memory cells are configured such that the plurality of data states comprise an error-prone data state. Sense circuitry of the apparatus is configured to sense first memory cells programmed to the error-prone data state, determine a bit encoding for the first memory cells, sense other memory cells programmed to other data states, and determine a bit encoding for the other memory cells. A communication circuit of the apparatus is configured to communicate the bit encoding for the other memory cells, the bit encoding for the first memory cells, and an indication that the first memory cells are programmed to the error-prone data state, in response to a single read command from a controller.Type: GrantFiled: September 28, 2018Date of Patent: August 4, 2020Assignee: SanDisk Technologies LLCInventors: Mostafa El Gamal, Jim Fitzpatrick
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Patent number: 10734071Abstract: Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.Type: GrantFiled: December 13, 2018Date of Patent: August 4, 2020Assignee: Western Digital Technologies, Inc.Inventors: Mostafa El Gamal, Niranjay Ravindran, James Fitzpatrick
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Patent number: 10705966Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.Type: GrantFiled: December 14, 2018Date of Patent: July 7, 2020Assignee: Western Digital Technologies, Inc.Inventors: Bernie Rub, Mostafa El Gamal, Niranjay Ravindran, Richard David Barndt, Henry Chin, Ravi J. Kumar, James Fitzpatrick