Abstract: A method for processing data flows of a plurality of passive optical network (PON) operating modes, the method is performed by an optical network unit (ONU). The method comprises processing upstream data flows of said plurality of PON operating modes; and processing downstream data flows of the plurality of PON operating modes. The plurality of PON operating modes include at least a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).

Abstract: A method for processing data flows of a plurality of passive optical network (PON) operating modes, the method is performed by an optical network unit (ONU). The method comprises processing upstream data flows of said plurality of PON operating modes; and processing downstream data flows of the plurality of PON operating modes. The plurality of PON operating modes include at least a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).

Abstract: An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).

Abstract: An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).

Abstract: A communication controller (111) for handling and processing data packets received from a large number of communication channels (181-188). The communication controller (111) comprising of: a processor (160) for processing data; a serial interface (28), coupled to the communication channels (181-188). A multi channel controller (100, 100′) coupled to the serial interface (28) and the processor (160), for interfacing between the communication channels (181-188) and the processor (160). The communication channels (181-188) and the serial interface (28) send and receive data packets. The processor (160) sends, receives and processes data words. The multi channel controller (100) receives data packets from the serial interface (28), concatenates data packets and sends data words to the processor (160). The multi channel controller (100) receives data words from the processor (160), and transmits data packets to the serial interface (28).

Abstract: A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two processors, second processor initializes first processor and handles high level management and protocol functions, first processor handles the data stream transactions. First processor and second processors are coupled to a two external buses. First processor handles a transactions of a frame by executing a task. First processor performs a task switch when there is a need to fetch information from an external unit, coupled to either first or second external bus, if it did process a whole frame, or if there is a need to fetch a portion of a frame from a communication channel.

Abstract: A multi-master bus system (10) comprises bus (12), a plurality of bus devices (14, 16, 18, 20, 22, 24), coupled to the bus, including masters (14, 16, 18), and slaves (20, 22, 24), a memory controller (26) for controlling the data exchange on bus (12), having a memory (36) for storing a transaction type value with respect to each slave (20, 22, 24). The multi-master bus system (10) comprises further an arbiter (30) for performing bus arbitration, arbiter (30) having logic for conditionally subsequently granting the bus (12) to a master of an initiating transaction for a closing transaction depending on the transaction type value of the slave of the initiating transaction. The multi-master bus system makes atomic or indivisible transactions possible on a bus without changing the bus width or the bus protocol.

Abstract: Output on Multiple Time Division Multiplexer (TDM) HDLC lines (28) is selectively and gracefully throttled. A throttling signal (99) is asserted whenever either the output FIFO queue (58) is almost full or the input FIFO queue (56) is almost empty. Whenever an in frame/out of frame state transition occurs for a given logical channel, a check is made whether throttling is required (292, 296). If throttling is required, an HDLC flag byte is transmitted (291, 299), delaying all such state transitions until the throttling signal (99) is no longer asserted.

Abstract: A clock system (2) for providing a system clock signal at a clock output (4) for use by a processing unit comprises a first oscillator circuit (6) which is enabled in response to a wake up signal provided by the processing unit to provide a first clock signal (RINGO CLOCK) at an output, and a second oscillator circuit (8) comprising a PLL (14) and an oscillator (16). The second oscillator (8) circuit provides a second clock signal (PLL CLOCK) and a lock signal (LOCKED) at first and second outputs respectively when the PLL is locked.

Abstract: A voltage spike detection circuit for use in detecting clock edge transitions utilizes a voltage change detection circuit (16) and a voltage spike latching circuit (18). The voltage change detection circuit (16) provides an output pulse in response to each edge transition of a serial communication clock, including an edge caused by a noise spike on the serial communication clock. In response to receiving the output pulse of the voltage change detection circuit (16), the voltage spike latching circuit (18) provides an active system interrupt signal to a serial communication system. When the serial communication system receives the active system interrupt signal, the serial communication system momentarily activates a system reset signal and re-communicates the serial communication data.

Abstract: A time slot assigner (20) for a serial communication system utilizes an encoded field of data. The time slot assigner (20) has a memory (52) for storing encoded data, a digital counter (60), a prescaler (62), a dedicated latch (58), and a time slot control logic (56). The enclosed data is partitioned into encoded data fields within the memory. A first encoded data field is utilized to indicate a last (LST) encoded data entry of a plurality of entries in the memory to be processed collectively, a second encoded data field (BRS) indicates a bit resolution of the data, a third encoded data field contains a count (CNT) value, and a fourth encoded data field selects a serial communication channel (CSEL). The time slot assigner (20) is activated by an active strobe start cycle signal, and is deactivated in response to a predetermined activated encoded data field.