Abstract: The present disclosure provides a motor drive device. The motor drive device includes a terminal, a logic unit, a drive unit and a determination unit. The terminal is configured to receive a Hall signal output from a Hall sensor. The logic unit is configured to generate a control signal based on the Hall signal. The drive unit is configured to generate a driving signal based on the control signal. The determination unit is configured to determine a level of a voltage applied to the terminal. The logic unit is configured to switch a function setting based on a determination result of the determination unit.

Abstract: The audio circuit has a volume circuit structured to process a DSD signal that contains DSD data and a DSD clock. The volume circuit has a first shift register and a replacement circuit. The first shift register holds N bits of the DSD data. The replacement circuit replaces (N?M) bits (0?M?N) corresponding to a gain set value, out of N bits stored in the first shift register, with a mute bit string having a mark rate of substantially 50%.

Abstract: A circuit configured to adjust the level of an audio signal includes filters each of which is configured to receive an audio signal, and to pass a band set for the filter. Variable gain amplifiers are severally provided to the respective filters, and each variable gain amplifier amplifies the output signal of the corresponding filter. An adder sums the input audio signal and the output signals of the variable gain amplifiers. A control unit controls the level of the output signal of each of the variable gain amplifiers, and controls the gain of each variable gain amplifier according to the level thus monitored.

Abstract: A first selector receives a second input signal and a second reference voltage, and selects either one. A first buffer receives the output signal of the first selector, and outputs the signal thus received to a terminal of the first resistor, and to a terminal of the third resistor. A second selector receives a first input signal and a third input signal, and selects either one. A fourth selector receives, as input signals, the output signal of an operational amplifier, a signal that corresponds to the output signal of the second selector, and a signal that corresponds to the second input signal, and selects one signal selected from among the signals thus received.

Abstract: A carrier offset detection circuit is offered, which is provided to a demodulation circuit which demodulates a received signal subjected to FSK (Frequency Shift Keying) modulation, and which detects the offset of the carrier frequency between the transmitting side and the receiving side. A zero-crossing detection unit receives a digital base band signal indicating the level of the frequency shift (frequency deviation) of the received signal using the carrier frequency on the receiving side as a reference frequency, and detects a zero-crossing point of the base band signal and a base band signal obtained by delaying the former base band signal by one symbol, which occurs in a preamble period. A carrier offset detection circuit sets the offset value of the carrier frequency to the value of the base band signal at a timing of the zero-crossing point thus detected.

Abstract: A circuit configured to adjust the level of an audio signal includes filters each of which is configured to receive an audio signal, and to pass a band set for the filter. Variable gain amplifiers are severally provided to the respective filters, and each variable gain amplifier amplifies the output signal of the corresponding filter. An adder sums the input audio signal and the output signals of the variable gain amplifiers. A control unit controls the level of the output signal of each of the variable gain amplifiers, and controls the gain of each variable gain amplifier according to the level thus monitored.

Abstract: A first selector receives a second input signal and a second reference voltage, and selects either one. A first buffer receives the output signal of the first selector, and outputs the signal thus received to a terminal of the first resistor, and to a terminal of the third resistor. A second selector receives a first input signal and a third input signal, and selects either one. A fourth selector receives, as input signals, the output signal of an operational amplifier, a signal that corresponds to the output signal of the second selector, and a signal that corresponds to the second input signal, and selects one signal selected from among the signals thus received.

Abstract: A carrier offset detection circuit is offered, which is provided to a demodulation circuit which demodulates a received signal subjected to FSK (Frequency Shift Keying) modulation, and which detects the offset of the carrier frequency between the transmitting side and the receiving side. A zero-crossing detection unit receives a digital base band signal indicating the level of the frequency shift (frequency deviation) of the received signal using the carrier frequency on the receiving side as a reference frequency, and detects a zero-crossing point of the base band signal and a base band signal obtained by delaying the former base band signal by one symbol, which occurs in a preamble period. A carrier offset detection circuit sets the offset value of the carrier frequency to the value of the base band signal at a timing of the zero-crossing point thus detected.