Abstract: A method of designing a layout of a semiconductor integrated circuit is provided. A logic simulation of a semiconductor integrated circuit to be designed is executed. A number of times of toggle operation of each of circuit elements constituting the semiconductor integrated circuit, which occurs during the execution of the logic simulation, is counted. A consumption power of the each of the circuit elements, determined based on the counted number of times of toggle operation thereof. Constraint conditions to be imposed on designing a layout of the circuit elements, are determined based on results of the estimation of the consumption power.

Abstract: A semiconductor integrated circuit is provided which has an internal core area in which a first set of transistors are regularly arranged, and a peripheral area in which a second set of transistors are arranged to constitute input/output circuits. In this semiconductor integrated circuit, the transistors arranged in the peripheral area include a plurality of transistors that are not used to constitute the input/output circuits, and these unused transistors constitute at least one driver for driving at least one of circuits constituted by the transistors arranged in the internal core area.