Patents by Inventor Motoaki Tani
Motoaki Tani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170243808Abstract: A joined body of the embodiments is a joined body which includes copper and resin, wherein in a joint surface of the copper to the resin, a triazine thiol derivative, or the triazine thiol derivative and a silane coupling agent are bonded to a base surface and the silane coupling agent is bonded to an oxide film formed on part of the joint surface, respectively, and the copper and the resin are molecularly joined to each other. This configuration makes it possible to obtain a joined body having high reliability by molecularly joining both the base surface and the oxide film of the copper, and the resin securely and achieving a strong joint of the copper and the resin at a time of joining the copper and the resin even though the oxide film is formed on part of the joint surface of the copper.Type: ApplicationFiled: May 10, 2017Publication date: August 24, 2017Applicant: FUJITSU LIMITEDInventors: MAKOTO YOSHINO, Takahiro Kimura, Motoaki Tani
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Patent number: 9318426Abstract: A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.Type: GrantFiled: March 6, 2013Date of Patent: April 19, 2016Assignees: FUJITSU LIMITED, FUJITSU TEN LIMITEDInventors: Motoaki Tani, Shinya Iijima, Shinichi Sugiura, Hiromichi Watanabe
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Patent number: 9312151Abstract: A method of manufacturing a semiconductor device, includes: providing a first adhesive layer on a support member; providing a film on the first adhesive layer; arranging a semiconductor element on the film; providing a resin layer on the film on which the semiconductor element is arranged, and forming a substrate including the semiconductor element and the resin layer on the film; and separating the film and the substrate from the first adhesive layer.Type: GrantFiled: January 24, 2013Date of Patent: April 12, 2016Assignee: FUJITSU LIMITEDInventors: Shinya Sasaki, Yoshikatsu Ishizuki, Motoaki Tani
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Patent number: 9214361Abstract: A method of manufacturing a semiconductor device, includes: placing a semiconductor element on an adhesive layer that is placed on a support body having a first through hole; placing a part in an area that includes a portion corresponding to the first through-hole, the portion being on the adhesive layer placed on the support body; forming a substrate on the adhesive layer by forming a resin layer on the adhesive layer, on which the semiconductor element and the part have been placed, the substrate including the semiconductor element, the part, and the resin layer; and detaching the substrate from the adhesive layer by pressing the part through the first through-hole.Type: GrantFiled: January 24, 2013Date of Patent: December 15, 2015Assignee: FUJITSU LIMITEDInventors: Yoshikatsu Ishizuki, Shinya Sasaki, Motoaki Tani
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Patent number: 9177938Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: GrantFiled: August 7, 2014Date of Patent: November 3, 2015Assignee: FUJITSU LIMITEDInventors: Motoaki Tani, Keishiro Okamoto
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Patent number: 9136172Abstract: A method of manufacturing a semiconductor device, includes: providing an adhesive layer on a support body; providing a semiconductor element on the adhesive layer; providing a resin layer on the adhesive layer, the semiconductor element being provided on the adhesive layer, and forming a substrate on the adhesive layer, the substrate including the semiconductor element and the resin layer; and removing the substrate from the adhesive layer, wherein an adhesive force of the adhesive layer in a direction in which the substrate is removed is less than an adhesive force of the adhesive layer in a planar direction in which the substrate is formed.Type: GrantFiled: January 23, 2013Date of Patent: September 15, 2015Assignee: FUJITSU LIMITEDInventors: Motoaki Tani, Yoshikatsu Ishizuki, Shinya Sasaki
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Publication number: 20150189751Abstract: A wiring board includes a conductor formed on an inner wall of a through hole made in a core board, resin formed inside the conductor in the through hole, and, for example, a land formed over the conductor and the resin. Vias are formed over the land. The vias are connected to a plurality of connection regions of the land extending over the conductor and the resin in the through hole. The land is held by the vias connected to the plurality of connection regions. This controls the thermal expansion of the resin to a land side and therefore prevents a fracture of the land.Type: ApplicationFiled: December 9, 2014Publication date: July 2, 2015Applicant: FUJITSU LIMITEDInventors: Tomoyuki AKAHOSHI, Daisuke Mizutani, Motoaki Tani
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Publication number: 20150171053Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: ApplicationFiled: August 7, 2014Publication date: June 18, 2015Applicant: FUJITSU LIMITEDInventors: Motoaki TANI, Keishiro OKAMOTO
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Patent number: 8866312Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: GrantFiled: January 26, 2012Date of Patent: October 21, 2014Assignee: Fujitsu LimitedInventors: Motoaki Tani, Keishiro Okamoto
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Patent number: 8420444Abstract: A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.Type: GrantFiled: February 16, 2011Date of Patent: April 16, 2013Assignees: Fujitsu Limited, Fujitsu Ten LimitedInventors: Motoaki Tani, Shinya Iijima, Shinichi Sugiura, Hiromichi Watanabe
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Patent number: 8318599Abstract: The resin layer formation method comprises the step of forming on a substrate 10 a resin layer 34 for containing a substance for decreasing the thermal expansion coefficient to thereby forming a resin layer 34 having said substance localized in the side thereof nearer to the substrate 10; and the step of cutting the surface of the resin layer 34 with a cutting tool 40 to planarize the surface of the resin layer 34. The resin layer 34 as said substance for decreasing the thermal expansion coefficient localized in the side thereof nearer to the substrate 10, and the surface of the resin layer 34 is cut to planarize the surface of the resin layer 34, whereby the extreme abrasion and breakage of the cutting tool 40 by said substance for decreasing the thermal expansion coefficient can be prevented.Type: GrantFiled: May 30, 2006Date of Patent: November 27, 2012Assignee: Fujitsu LimitedInventors: Kanae Nakagawa, Motoaki Tani
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Publication number: 20120217660Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: ApplicationFiled: January 26, 2012Publication date: August 30, 2012Applicant: FUJITSU LIMITEDInventors: Motoaki TANI, Keishiro Okamoto
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Publication number: 20120085730Abstract: A method for manufacturing a wiring board, includes: forming an insulating resin layer on a conductive layer; forming a metal chloride or a metal sulfate on the insulating resin layer; forming a protective layer on the metal chloride or the metal sulfate; forming an exposed portion in the insulating resin layer, the metal chloride or the metal sulfate, and the protective layer so as to at least partially expose the conductive layer; removing residues in the exposed portion; removing the protective layer; and forming a wiring on the insulating resin layer in which the protective layer has been removed.Type: ApplicationFiled: December 15, 2011Publication date: April 12, 2012Applicant: FUJITSU LIMITEDInventors: Shinya SASAKI, Motoaki TANI
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Publication number: 20110233765Abstract: A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.Type: ApplicationFiled: February 16, 2011Publication date: September 29, 2011Applicants: FUJITSU LIMITED, FUJITSU TEN LIMITEDInventors: Motoaki TANI, Shinya Iijima, Shinichi Sugiura, Hiromichi Watanabe
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Patent number: 7799604Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.Type: GrantFiled: July 2, 2007Date of Patent: September 21, 2010Assignee: Fujitsu LimitedInventors: Tomoyuki Abe, Motoaki Tani
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Patent number: 7640660Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).Type: GrantFiled: April 19, 2007Date of Patent: January 5, 2010Assignee: Fujitsu LimitedInventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani
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Publication number: 20090218118Abstract: A board includes a core board, an electronic component arranged on the core board, and an intermediate layer that includes resin containing carbon fibers and that surrounds the electronic component from the side.Type: ApplicationFiled: February 26, 2009Publication date: September 3, 2009Applicant: FUJITSU LIMITEDInventor: Motoaki TANI
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Patent number: 7420130Abstract: The wiring board comprises a plate-shaped conductive core material 10 with a through-hole 12 formed in, an insulation layer 14 formed on the surface of the conductive core material 10 and on the inside wall of the through-hole 12, a resin 18 buried in the through-hole 12 with the insulation layer 14 formed in, wirings 22a, 22b formed on the upper surface and the undersurface of the conductive core material 10 with the insulation layer 14 formed on, and an wiring 22d formed in the through-hole 20 formed in the resin 18 and electrically connected to the wirings 22a, 22b.Type: GrantFiled: June 15, 2007Date of Patent: September 2, 2008Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Tomoyuki Abe, Motoaki Tani, Nobuyuki Hayashi
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Patent number: 7400035Abstract: A semiconductor device includes a support body, a first substrate provided on a surface at one side of the support body, a second substrate provided on a surface at the other side of the support body, and a semiconductor chip provided on the first substrate exposed to an opening part piercing the support body and the second substrate. The first substrate includes a first dielectric layer and a wiring layer, a plurality of first electrodes connected to the semiconductor chip which first electrodes are provided on a first surface of the first substrate exposed to an inside of the opening part, and the second substrate includes a second dielectric layer made of a material substantially the same as the first dielectric layer.Type: GrantFiled: December 28, 2004Date of Patent: July 15, 2008Assignee: Fujitsu LimitedInventors: Tomoyuki Abe, Motoaki Tani
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Patent number: 7388157Abstract: A printed wiring board is made of first and second substrates superimposed on each other. The first and second substrates respectively include a core layer made of resin containing carbon fibers. The second substrate has the outline different from that of the first substrate. A stepped surface is defined on the front surface at least of the first substrate. Electrodes can be formed on the stepped surface as well as on the back surface of the first substrate and the front surface of the second substrate. This structure enables detection of an electric signal from the stepped surface. A further flexibility can thus be achieved in locating electrodes as compared with a conventional printed wiring board having uniform substrates simply superimposed on each other. This results in an expanded use or purpose for a printed wiring board.Type: GrantFiled: December 30, 2005Date of Patent: June 17, 2008Assignee: Fujitsu LimitedInventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani, Kenichiro Abe, Kenji Iida