Abstract: A capacitance measurement method is provided which is capable of measuring an accurate capacitance value even if a leakage current on a level that cannot be ignored occurs in a capacitance to be measured. In step S1, a test current ICnorm is measured by using a normal PMOS gate potential as a PMOS gate potential for providing on/off control of PMOS transistors in a predetermined cycle. In step S2, a current ICrat is measured by using, as the PMOS gate potential, a multiplied on-time PMOS gate potential, the “L” period and fall time of which are integral multiples of those of the normal PMOS gate potential. In step S3, based on the currents ICnorm, ICrat, a leakage current IRt is eliminated and the amount of capacity current CIC consisting only of a capacitance current component ICt is calculated. In step S5, a target capacitance is obtained based on the capacity current CIC and a charge frequency frat obtained in step S4.

Abstract: A capacitance measurement method is provided which is capable of measuring an accurate capacitance value even if a leakage current on a level that cannot be ignored occurs in a capacitance to be measured. In step S1, a test current ICnorm is measured by using a normal PMOS gate potential as a PMOS gate potential for providing on/off control of PMOS transistors in a predetermined cycle. In step S2, a current ICrat is measured by using, as the PMOS gate potential, a multiplied on-time PMOS gate potential, the “L” period and fall time of which are integral multiples of those of the normal PMOS gate potential. In step S3, based on the currents ICnorm, ICrat, a leakage current IRt is eliminated and the amount of capacity current CIC consisting only of a capacitance current component ICt is calculated. In step S5, a target capacitance is obtained based on the capacity current CIC and a charge frequency frat obtained in step S4.

Abstract: An error function S is defined by dividing the square of the difference between each of the characteristic quantities &sgr;iy and corresponding the function fy (vi, P) by variance &sgr;iy2 of observed values from a plurality of samples and summing the quotients for the plural number of extrinsic factor sets. It is possible to correct the effects of variation and bias of the observed values included in the error factor with division by the variance &sgr;iy2 for each of the characteristic quantities even when there is a variation in size among the values of the error factors in the characteristic quantities. Further, it is verified whether the function fy (vs, P) reproduces the observed values by utilizing conformity of the value of the error function S to &khgr;2 distribution and when it is verified that the function fy (vs, P) reproduces the observed values, the parameter set P at that time is extracted as one that gives the minimum value of the error function S.

Abstract: A method of and device for simulation which represents variations in electrical characteristics (Idsat, Vth and the like) of a device constituting a semiconductor integrated circuit in the form of a corner model including corners defining the limits of the variations is provided. A circuit simulation is performed to determine device parameter sensitivities which are the derivatives of the electrical characteristics with respect to device parameters such as &Dgr;L, &Dgr;W, Tox and Vth0. Variations in the device parameters at each corner are determined by applying the device parameter sensitivities and the values of the electrical characteristics required for each corner to the normal equation of the linear least squares method. The method and device can determine the values of a set of device parameters at each corner without the need to repeat the circuit simulation and can uniquely determine the values of the set of device parameters.

Abstract: In a method of simulating hot carrier deterioration of an MOS transistor,.DELTA.I.sub.D /I.sub.D =(.DELTA.I.sub.D /I.sub.D).sub.f .multidot.(W.multidot.B).sup.-n .multidot.I.sub.SUB.sup.mn .multidot.I.sub.D.sup.(1-m)n .multidot.t.sup.n.DELTA.I.sub.D /I.sub.D =(.DELTA.I.sub.D /I.sub.D).sub.f .multidot.B.sup.-n .multidot.W.sup.-mn .multidot.I.sub.G.sup.mn .multidot.t.sup.nis used in the simulation for a P-MOS transistor, where B is a constant, W is a gate width, I.sub.SUB is a substrate current, I.sub.D is a drain current, t is a time, I.sub.G is a gate current, n is represented by a function g=(V.sub.G, V.sub.D), and V.sub.G and V.sub.D represent a gate voltage and a drain voltage, respectively.